2020
DOI: 10.1063/1.5141391
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A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array

Abstract: A field-programmable-gate-array (FPGA) based time-to-digital-converter (TDC), which combines different types of delay chains in a single time measurement channel, is reported in this paper. A new TDC architecture is developed, and both a carry-chain and the DSP48E1 adders, which are integrated inside the FPGA chip, are employed to achieve high resolution time tagging. A single channel TDC has a 3.3 ps averaged bin size, a 5.4 ps single-shot precision, and a maximum sampling rate of 250 MSa/s. The differential-… Show more

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Cited by 19 publications
(12 citation statements)
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“…In contrast, consider the calibrations and requirements of other TDC architectures: bin-realignment, statistical tests, coding-decoding, sorting algorithms, individual carry calibrations, etc. [3], [5]- [7], [9]- [11], [17], [28]- [30]. In Ref.…”
Section: Case Study: Asynchronous Ring-oscillatormentioning
confidence: 99%
See 1 more Smart Citation
“…In contrast, consider the calibrations and requirements of other TDC architectures: bin-realignment, statistical tests, coding-decoding, sorting algorithms, individual carry calibrations, etc. [3], [5]- [7], [9]- [11], [17], [28]- [30]. In Ref.…”
Section: Case Study: Asynchronous Ring-oscillatormentioning
confidence: 99%
“…Using this approach, TDCs have been realized with few ps resolution [5]- [7]. However, calibrating the FPGA-TDCs is challenging because it is difficult to generate ps-scale signals on the chip.…”
Section: Introductionmentioning
confidence: 99%
“…In previous studies, the FPGA-based TDCs barely used the digital-signal-processor (DSP) resources for time interpolating, whereas the utilization of DSP slices in the FPGA can contribute to an efficient solution to realize high resolution time measurement [30,31]. In our previous study [32], an FPGA-based TDC which combines the carry chain and the DSP-based delay chain in a single time measurement channel is reported. However, there remains a number of invalid bins inside the DSP chain, thus new TDC designs can be investigated to improve the TDC performance.…”
Section: Motivationmentioning
confidence: 99%
“…Many architectures and methods, including the dual-sampling structure, the Vernier delay line, the multi-phase design, the multi-chain design and the wave-union method, were proposed to overcome process-related limitations improve TDC resolutions [31]- [35]. Other logic resources, for example, routings and digital signal processing (DSP) blocks, can also be used to build TDCs [36], [37].…”
Section: Introductionmentioning
confidence: 99%