A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array

Qin, Xi; Zhu, Ming-Dong; Zhang, W.; Lin, Yiheng; Rui, Ying; Rong, Xing; Du, Jiangfeng

doi:10.1063/1.5141391

Cited by 19 publications

(12 citation statements)

References 28 publications

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“…In contrast, consider the calibrations and requirements of other TDC architectures: bin-realignment, statistical tests, coding-decoding, sorting algorithms, individual carry calibrations, etc. [3], [5]- [7], [9]- [11], [17], [28]- [30]. In Ref.…”

Section: Case Study: Asynchronous Ring-oscillatormentioning

confidence: 99%

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High-Resolution Waveform Capture Device on a Cyclone-V FPGA

2021

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We introduce the waveform capture device (WCD), a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD is implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA, Intel/Altera Cyclone V), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It is calibrated via a novel dynamic phase-shifting (DPS) method that requires substantially less data and resources than the state-of-the-art. Using DPS, we find the measurement resolution -or mean propagation delay from one CC element to the next -to be 4.91±0.04 ps (4.54±0.02 ps) for a pulse of logic high (low). Similarly, we find the single-shot precision -or mean error on the timing of the waveform -to be 29.52 ps (27.14 ps) for pulses of logic high (low). We verify these findings by reproducing commercial oscilloscope measurements of asynchronous ring-oscillators on FPGAs, finding the mean pulse width to be 0.240 ± 0.002 ns per inverter gate. Finally, we present a careful analysis of design constraints, introduce a novel error correction algorithm, and sketch a simple extension to the analog domain. We also provide the Verilog code instantiating our design's hardware primitives in an Appendix, and make our FPGA interfacing methods available as an open-source Python library at https://github.com/Noeloikeau/fpyga.

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Section: Case Study: Asynchronous Ring-oscillatormentioning

confidence: 99%

“…Using this approach, TDCs have been realized with few ps resolution [5]- [7]. However, calibrating the FPGA-TDCs is challenging because it is difficult to generate ps-scale signals on the chip.…”

Section: Introductionmentioning

confidence: 99%

High-Resolution Waveform Capture Device on a Cyclone-V FPGA

2021

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“…In previous studies, the FPGA-based TDCs barely used the digital-signal-processor (DSP) resources for time interpolating, whereas the utilization of DSP slices in the FPGA can contribute to an efficient solution to realize high resolution time measurement [30,31]. In our previous study [32], an FPGA-based TDC which combines the carry chain and the DSP-based delay chain in a single time measurement channel is reported. However, there remains a number of invalid bins inside the DSP chain, thus new TDC designs can be investigated to improve the TDC performance.…”

Section: Motivationmentioning

confidence: 99%

A time-to-digital-converter utilizing bits-counters to decode carry-chains and DSP48E1 slices in a field-programmable-gate-array

et al. 2021

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This paper presents the implementation of a field-programmable-gate-array based high-resolution time-to-digital converter, which utilizes the carry-chains and the digital-signal-processor slices for time interpolating. Bits-counter decoders are employed to manage the output codes from both the carry-chains and the digital-signal-processor slices, in order to achieve a high utilization rate of the time interpolating cells. A single channel TDC has a 2.03 ps averaged bin size and a 2.8 ps single-shot precision. The differential-non-linearity (DNL) of the single channel TDC is −1.82 ps/+12.56 ps, and the integral-non-linearity (INL) is within −6.55 ps/+47.95 ps. The TDC performance can be further improved by implementing multiple chains in a single time measurement channel, and a 2.2 ps single-shot precision is obtained by employing four parallel channels to measure the same input signal. The reported TDC can achieve a better precision with less resources comparing to previous studies, therefore the reported architecture is favorable for those applications that require high resolution multichannel time measurements.

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“…Many architectures and methods, including the dual-sampling structure, the Vernier delay line, the multi-phase design, the multi-chain design and the wave-union method, were proposed to overcome process-related limitations improve TDC resolutions [31]- [35]. Other logic resources, for example, routings and digital signal processing (DSP) blocks, can also be used to build TDCs [36], [37].…”

Section: Introductionmentioning

confidence: 99%

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

Xie

Wang

Chen

et al. 2022

IEEE Trans. Ind. Electron.

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This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue highlinearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in fieldprogrammable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged − and − are close to or even less than 0.05 LSB in multichannel designs. Index Terms-Light detection and ranging (LiDAR), Timeto-digital converters (TDCs), Time-of-flight (ToF), Fieldprogrammable gate arrays (FPGAs)

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A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array

Cited by 19 publications

References 28 publications

High-Resolution Waveform Capture Device on a Cyclone-V FPGA

High-Resolution Waveform Capture Device on a Cyclone-V FPGA

A time-to-digital-converter utilizing bits-counters to decode carry-chains and DSP48E1 slices in a field-programmable-gate-array

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

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