2021
DOI: 10.1088/1748-0221/16/02/p02009
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A time-to-digital-converter utilizing bits-counters to decode carry-chains and DSP48E1 slices in a field-programmable-gate-array

Abstract: This paper presents the implementation of a field-programmable-gate-array based high-resolution time-to-digital converter, which utilizes the carry-chains and the digital-signal-processor slices for time interpolating. Bits-counter decoders are employed to manage the output codes from both the carry-chains and the digital-signal-processor slices, in order to achieve a high utilization rate of the time interpolating cells. A single channel TDC has a 2.03 ps averaged bin size and a 2.8 ps single-… Show more

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Cited by 8 publications
(3 citation statements)
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“…Amiet et al [19] designed a hardware architecture that supports arbitrary prime fields up to 1024 bits and different standards of ECSM. The processor needs 1.49 ms to realize 256-bit multiplication over the prime field with 20 DSPs and 6816 LUTs, which has excellent performance.…”
Section: Results and Comparison Pmentioning
confidence: 99%
See 1 more Smart Citation
“…Amiet et al [19] designed a hardware architecture that supports arbitrary prime fields up to 1024 bits and different standards of ECSM. The processor needs 1.49 ms to realize 256-bit multiplication over the prime field with 20 DSPs and 6816 LUTs, which has excellent performance.…”
Section: Results and Comparison Pmentioning
confidence: 99%
“…The core idea of SCA is to obtain ciphertext from various leaked information generated during hardware operations [17]. Some works [18], [19] use binary expansion algorithm in the implementation of ECSM. In this algorithm, whether the point addition (PA) operation is performed depends on the binary string of the key, so this method has low immunity to SCAs, such as the power analysis attack.…”
Section: Introductionmentioning
confidence: 99%
“…In a ToT circuit, the difference between two time stamps where the signal crosses a pre-defined threshold is stored. This can be implemented with time to digital conversion [152,153]. Integration of readout electronics and digital SiPM, within a single chip can make them noisier than analog SiPMs.…”
Section: Energy Measurementsmentioning
confidence: 99%