A high-performance MOS technology for 16K static RAM

OVER THE PAST FEW YEARS, there has been a groundswell of support for the use of redundancy in memory components. Redundancy may be the new innovation factor which allows bit density to continue growing at the traditional rate of 2X/year. Previous papers have described redundancy techniques for dynamic RAMS-' and other memory components3 where speed is not the primary goal. This paper will describe techniques utilized in a 40ns 16KX1 static RAM.ent technological factors and random run-to-run process defect distributions. For this 16K static RAM4, area ratios and layout density are such that peripheral circuits such as input and output buffers fail rarely and when they do, are often unrepairable. Thus attention was immediately focused on the failure modes of the memory array and its associated row and column decoders. There are several alternatives for repairing array-associated defects. These methods are best described by stating the group size of the spare repair elements, as shown in Table 1. Spare rows and columns are chosen as the best compromise between modularity and flexibility. Further analysis of the 16K static RAM technology5 indicates that spare rows provide the biggest payoff, since the polysilicon (word line and single bit) design rules are more aggressive than the metal and contact (bit line) design rules.This decision made the circuit design more difficult since the row decoders are in the critical access path whereas the column decoders have much looser speed requirements. As a result, new techniques were developed t o minimize the speed impact of redundancy.Goals for the redundancy circuits are: minimize speed/power impact, minimize added die area, allow convenient programming of fuses at wafer probe, and maximize circuit reliability.The address of a faulty element is programmed into the spare element by electrically blowing polysilicon fuses during wafer probe. The basic circuit block diagram for a spare row is shown Device failure modes are a function of the chip layout, inher-__ bdenum-Polysilicon Technology," ISSCC DIGEST O F TECH-

show abstract

A high performance sense amplifier for a 5 V dynamic RAM

Barnes¹,

Chan²

1980

IEEE J. Solid-State Circuits

View full text Add to dashboard Cite

A high-performance MOS technology for 16K static RAM

Cited by 9 publications

References 2 publications

A high speed 2k &#215; 8 bit NMOS static RAM with a new double poly-Si gate memory cell process

A high speed 2k &#215; 8 bit NMOS static RAM with a new double poly-Si gate memory cell process

Redundancy techniques for fast static RAMs

A high performance sense amplifier for a 5 V dynamic RAM

Contact Info

Product

Resources

About

A high-performance MOS technology for 16K static RAM

Cited by 9 publications

References 2 publications

A high speed 2k &amp;#215; 8 bit NMOS static RAM with a new double poly-Si gate memory cell process

A high speed 2k &amp;#215; 8 bit NMOS static RAM with a new double poly-Si gate memory cell process

Redundancy techniques for fast static RAMs

A high performance sense amplifier for a 5 V dynamic RAM

Contact Info

Product

Resources

About

A high speed 2k × 8 bit NMOS static RAM with a new double poly-Si gate memory cell process

A high speed 2k × 8 bit NMOS static RAM with a new double poly-Si gate memory cell process