A high performance current mirror for low voltage designs

Rajput, Shyam Singh; Jamuar, Sudhanshu Shekhar

doi:10.1109/apccas.2000.913434

Cited by 35 publications

(13 citation statements)

References 9 publications

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“…The advantage offered by se structure is that it offers higher output impedance than a regular cascode structure while output voltage requirements are similar to that of single transistor [15,16]. The comparison of V-I characteristics of SCCM-2: This proposed LVCM is shown in Figure 14.…”

Section: Self Cascode Technique For LV Topologiesmentioning

confidence: 99%

Self Cascode: A Promising Low Voltage Analog Design Technique

Kaur

Prakash

Rajput

2009

IETE Journal of Education

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Section: Self Cascode Technique For LV Topologiesmentioning

confidence: 99%

Self Cascode: A Promising Low Voltage Analog Design Technique

Kaur

Prakash

Rajput

2009

IETE Journal of Education

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“…To obtain this ideal condition the input impedance should be zero, output impedance should be infinite and output current should be constant over wide swing of voltages [2]. Many topologies have been presented earlier to improve the current mirror performance some of which include, Level-shifter technique [3,4], FGMOS technique [5,6], Bulk-driven technique [7,8,9]. Level shifter technique requires additional circuitry to compensate offset hence increasing power requirements of the overall circuit.…”

Section: Introductionmentioning

confidence: 99%

Noise and Bandwidth analysis for PMOS based wide swing cascode current mirror using 0.35 um CMOS-MEMS technology

Mian

Dennis

Khir

et al. 2014

2014 5th International Conference on Intelligent and Advanced Systems (ICIAS)

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In this work, we propose a PMOS based wide swing cascode current mirror (WSSCM) for 0.35 um CMOS-MEMS technology. The proposed circuit shows a high bandwidth current mirror with high output resistance capability operating at low voltage levels. Noise, output resistance and bandwidth analysis are presented. CADENCE SPECTRE circuit design tool using MIMOS 0.35 um and BSIM3 transistor models is used to carry out the simulations. The circuit achieves an amplification of 120.04 uA, the input referred noise of the circuit is 75.77 nV/√Hz with a minimum power consumption of 0.33 mW and a high output resistance of 15 M Ω .

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“…High performance current mirrors operating at such low input and output voltages are required as building blocks of mixed mode VLSI systems that operate from a single supply of 1.5 V or less [1].…”

Section: Introductionmentioning

confidence: 99%

Low voltage current mirrors with enhanced bandwidth

Gupta

Aggarwal

Singh

et al. 2008

Analog Integr Circ Sig Process

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This paper presents an improved low voltage cascode and flipped voltage follower (FVF) based current mirror with the enhancement of the bandwidth obtained by using a compensation resistor between the gates of the primary transistor pair. In this technique a carefully determined resistance is used in the diode connected MOS transistor of the current mirror for enhancing the bandwidth. Active realization of the compensation resistance using MOS operating in the triode region has also been applied to both the cascode and FVF based current mirror circuits. The proposed circuits have been simulated using PSpice for 0.25 lm CMOS technology and the obtained results are compared with their uncompensated topologies to show their effectiveness.

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A high performance current mirror for low voltage designs

Cited by 35 publications

References 9 publications

Self Cascode: A Promising Low Voltage Analog Design Technique

Self Cascode: A Promising Low Voltage Analog Design Technique

Noise and Bandwidth analysis for PMOS based wide swing cascode current mirror using 0.35 um CMOS-MEMS technology

Low voltage current mirrors with enhanced bandwidth

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