A scaled double-poly MOS technology has been developed which features a static memory cell size of 1.5 mil2 with 4p design rules using conventional photolithographic techniques. The technology scales the gate oxide thickness to 4008 and polySi channel length to 2.11-1 with arsenic source-drain and self-aligned poly-poly via contact. Four different types of transistors are implemented to enhance circuit design versatility. Hot electron failures and soft errors do not limit the applicability of the technology.