A high-performance 0.1 μm CMOS with elevated salicide using novel Si-SEG process

Abstract

Figure 2 shows good cut-off characteristics obtained for 0.12 p m CMOS devices with subthreshold slopes Abstract High-performance O" /an devices with of 89 mV/dec and 103 ,)rrV/dec for nfilOSFET and vated for gate and source/drain pT\!IOSFET, respectively. Although the gate currents (S/D) regions and 80-n7n gate side-wa11 have been (IG) by direct tunneling through 2.5-7tm gate oxide demonstrated by a novel silicon selective epitaxial growth (SEG) process.film are observed for nMOSFETs, IG is much smaller than subthreshold leakage current. High saturation Both junction leakage current-and bridging between the gate and S/D drive currents are observed a 0.58 mn,A/lLm and 0.39 ,,nA/CL1,2 for nA,fOSFET and phIOSFET at VG = V D regions are by this high-quality and selective Si-SEG process. The elevated-salicide 0.1-pn CMOS devices have high reliability and high drive current, and are suitable for future high-performance logic LSIS. = 1.5 v, respectively, as shown in Fig. 3. Furthermore, normal ID-vD characteristics of the o.08 C"r?~ CMOS devices were also performed, as shown in Fig. 4. Short channel effects for n/pMOSFETs with side wall of 80-wtn thickness are well suppressed because of shallower S/D extensions and S/D regions by the low-energy arsenic and BF2 I/I. However, in these shallow S/D extensions and S/D regions, severe junction leakage currents are observed for shallower n+-p junctions than p+-n junctions, because of the conventional salicide film formation without an elevated structure, as shown in Fig. 6. Therefore, it is clear that the elevated salicide structure should be investigated to suppress the p-n junction leakage current.Introduction 0.1 C L I~ CMOS devices are investigated for highperformance logic LSIs [l, 2, 31. One of the key issues for the high-performance 0.1 pm, CMOS devices with salicide film is the trade-off between S/D junction depth and salicide film thickness. Although the elevated salicide technology is one of the candidates [.1, 51, it is difficult to suppress both p-n junction leakage current with low-resistance salicide film and electrical bridging through gate side wall between the gate electrode and S/D regions for 0.1 pm h4OSFETs which have thinner side-wall film. vices were demonstrated by using elevated salicide struc-elevated salicide structure should be formed uniformly ture. In order to form high-quality epitaxial silicon with high-quality SEG-Si film. It has been reported Novel Silicon Selective Epitaxial Growth In this paper, high-performance o'l lLm deIn order to reduce p-n junction leakage current, the and salicide a Si-SEG pro-that the SEG-Si film quality is very sensitive to the pre-treatment process of wet cleaning and the in-situ was with both low p-n junction lealiage thermal flashing before the Si-SEG process [5]. Furthermore, in order to achieve highly-selective Si growth between the Si substrate and the Si02 film, the Si-SEG process was carried out under reaction-limited conditions at 660 "C with 1 SCCM Si2HG gas, as shown in Fig. 7 (a). However the surface mor...

Growth of Selective Silicon Epitaxy Using Disilane and Chlorine on Heavily Implanted Substrates: II. Role of Implanted Arsenic

“…More recently, however, with the need for ultrashallow source/drain junction depths in future MOSFETs, sacrificial layers deposited prior to silicidation have been proposed in order to prevent the occurrence of junction consumption during device fabrication. 13 As a result, the effects of arsenic implants on subsequent silicon epitaxial growth have become extremely pertinent.…”

“…The effectiveness of this low thermal budget in situ clean has been demonstrated in prior work by Çelik. 13 Silicon deposition was controlled by temperature switching during which the temperature ramp rates achieved by the arc lamp have been approximated at around 150ЊC/s. Typical conditions for epitaxial growth utilized 130 standard cubic centimeters per minute (sccm) of 10% disilane in helium, a growth pressure of 40 mTorr, and a growth temperature of 800ЊC.…”

Quality of Selective Silicon Epitaxial Films Deposited Using Disilane and Chlorine

“…As an alternative to conventional silicon epitaxy, low-temperature selective silicon epitaxial growth (SEG) is presently being considered for several applications in ultralarge-scale in process integration. [1][2][3] Ideally, during SEG the process chemistry is such that nucleation does not occur on the insulator surface, while epitaxial growth is not significantly inhibited. Additionally, the epitaxial layers ideally exhibit minimal structural defects, since these imperfections can lead to degradations in electrical device performance.…”

Reduction of Leakage Current for Shallow n + / p Junction Fabricated Using C49 TiSi2 as a Diffusion Source

“…The n ϩ /p junctions have more severe problems with regard to junction leakage than p ϩ /n by reason of a shallower junction. 4 To overcome the limitations of forming Ti-silicided shallow junctions, Kwong 5 and Rubin 6 reported on a technique for silicided shallow junction formation using implantation of suitable impurity ions through silicide layers followed by drive-in. In each case, the drive-in was performed as high as 900ЊC by furnace annealing or 1000ЊC by rapid thermal annealing (RTA).…”