A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Lindner, Scott; Pellegrini, Sara; Henrion, Y.; Rae, Bruce R.; Wolf, M.; Charbon, Edoardo

doi:10.1109/led.2017.2755989

Cited by 68 publications

(36 citation statements)

References 11 publications

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“…36 Nonetheless, its overuse of area and power make it not appealing to exploit in SPADs front end. Regarding the area, 35 has the least area. Its hold-off time implementation is same as 16 , and off-chip pin is used to reduce area.…”

Section: Resultsmentioning

confidence: 99%

Low‐power compact tunable quenching configuration for minimizing afterpulsing in single‐photon avalanche diodes

Pahlavanzadeh

Karami

2020

Circuit Theory & Apps

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Summary This paper unveils two efficient free running (FR) quenching circuits with the aim of reducing quenching time (QT) to minimize avalanche charge. Likewise, one circuit is compactly designed with low power consumption, suitable for single‐photon avalanche diode (SPAD) with hold‐off time below 10 ns. In second circuit, tunable hold‐off and reset‐time are provided within a wide range without decreasing QT, which are desirable in many applications. Proper operation and circuit uncertainty is assessed by Monte Carlo analysis in a standard 90‐nm complementary metal‐oxide semiconductor (CMOS) technology. In a bid to do a comparison between previously reported circuits and the proposed circuits, they are simulated with same SPAD model and parameters and results corroborate the proposed circuits guarantee active quenching time (AQT) of below 1 ns. Proposed circuits with current and area consumption of 0.74 μA, 32 μm2 for 7‐ns dead time and 16.2 μA, 93 μm2 for 21‐ns dead time are more efficient in terms of QT, area, and power consumption in comparison with other works.

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Section: Resultsmentioning

confidence: 99%

Low‐power compact tunable quenching configuration for minimizing afterpulsing in single‐photon avalanche diodes

Pahlavanzadeh

Karami

2020

Circuit Theory & Apps

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“…The sensor employs a SPAD with a p-i-n structure reported in [ 17 ]. In order to achieve both high PDP and fill factor, a cascoded quenching circuit, Figure 2 , is used to allow the SPAD to operate at excess bias voltages up to 5.2 V without exceeding the 3.6 V reliability limit across the gate-source, gate-drain and drain-source junctions of any device [ 18 ]. Since this technique only uses transistors, the layout is very dense, achieving an overall fill factor of 28% with a pixel pitch of 28.5 μm.…”

Section: Sensor Designmentioning

confidence: 99%

A CMOS SPAD Imager with Collision Detection and 128 Dynamically Reallocating TDCs for Single-Photon Counting and 3D Time-of-Flight Imaging

Zhang

Lindner

Antolović

et al. 2018

Sensors

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Per-pixel time-to-digital converter (TDC) architectures have been exploited by single-photon avalanche diode (SPAD) sensors to achieve high photon throughput, but at the expense of fill factor, pixel pitch and readout efficiency. In contrast, TDC sharing architecture usually features high fill factor at small pixel pitch and energy efficient event-driven readout. While the photon throughput is not necessarily lower than that of per-pixel TDC architectures, since the throughput is not only decided by the TDC number but also the readout bandwidth. In this paper, a SPAD sensor with 32 × 32 pixels fabricated with a 180 nm CMOS image sensor technology is presented, where dynamically reallocating TDCs were implemented to achieve the same photon throughput as that of per-pixel TDCs. Each 4 TDCs are shared by 32 pixels via a collision detection bus, which enables a fill factor of 28% with a pixel pitch of 28.5 μm. The TDCs were characterized, obtaining the peak-to-peak differential and integral non-linearity of −0.07/+0.08 LSB and −0.38/+0.75 LSB, respectively. The sensor was demonstrated in a scanning light-detection-and-ranging (LiDAR) system equipped with an ultra-low power laser, achieving depth imaging up to 10 m at 6 frames/s with a resolution of 64 × 64 with 50 lux background light.

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“…Hybrid Cu-Cu bonding offers a mass-manufacturable platform to implement these sensors by providing high fill-factor SPADs optimized for NIR stacked on dense nanoscale digital processors [4][5] [6].…”

Section: Introductionmentioning

confidence: 99%

A Reconfigurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LIDAR or High-Speed Time-of-Flight Imaging

Hutchings

Johnston

Gyöngy

et al. 2019

IEEE J. Solid-State Circuits

147

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A 256 x 256 single photon avalanche diode (SPAD) sensor integrated in a 3D-stacked 90nm 1P4M/40nm 1P8M process is reported for flash light detection and ranging (LIDAR) or high speed direct time of flight (ToF) 3D imaging. The sensor bottom tier is composed of a 64x64 matrix of 36.72 m pitch modular photon processing units which operate from shared 4x4 SPADs at 9.18 m pitch and 51% fill-factor. A 16 x 14-bit counter array integrates photon counts or events to compress data to 31.4 Mbps at 30 fps readout over 8 I/O operating at 100 MHz. The pixel-parallel multi-event TDC approach employs a programmable internal or external clock for 0.56 ns to 560 ns time bin resolution. In conjunction with a perpixel correlator, the power is reduced to less than 100 mW in practical daylight ranging scenarios. Examples of ranging and high speed 3D TOF applications are given. Index Terms-3-D imaging, CMOS, direct time of flight (dTOF), histogramming, image sensor, light detection and ranging (LiDAR), single photon avalanche diodes (SPADs), time-to-digital converter (TDC), TDC sharing architecture, TOF.

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A High-PDE, Backside-Illuminated SPAD in 65/40-nm 3D IC CMOS Pixel With Cascoded Passive Quenching and Active Recharge

Cited by 68 publications

References 11 publications

Low‐power compact tunable quenching configuration for minimizing afterpulsing in single‐photon avalanche diodes

Low‐power compact tunable quenching configuration for minimizing afterpulsing in single‐photon avalanche diodes

A CMOS SPAD Imager with Collision Detection and 128 Dynamically Reallocating TDCs for Single-Photon Counting and 3D Time-of-Flight Imaging

A Reconfigurable 3-D-Stacked SPAD Imager With In-Pixel Histogramming for Flash LIDAR or High-Speed Time-of-Flight Imaging

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