A high density 0.10 μm CMOS technology using low K dielectric and copper interconnect

Parihar, Shivendra Singh; Angyal, M.; Boeck, B.; Reber, D.; Singhal, A.; Gompel, T. Van; Li, R.; Wilson, B. J.; Wright, Mike; Chen, J.; Grudowski, P. A.; Jeon, Young‐Jin; Qi, Wen Jie; Bai, Xiaoliang; Parker, L.; Strozewski, Kirk J.; Smith, Dave A.; Roling, S.; Sparks, T.; Stephens, T.; Huang, Fanyang; Mora, R.; Aminpur, M.; Hellig, K.; Vishnubhotla, L.; Solomentsev, Yuri; Arunachalam, V.; Phillips, Andrew; Junker, K.; Filipiak, S.; Ramani, N.; Turner, M.; Rendon, Mateo; Molloy, J.; McGuffin, K.; Michel, A. E.; Capilla, Rafael Peña; Rose, Doug; Schmidt, J.; Smith, M.; Wilson, Matthew S.; Terpolilli, L.; Le, Phuong; Sun, J.Y.-C.; Ross, Ryan; Yu, Katie; Hall, Michael J.; Ingersoll, P.; Woo, M.; Yeap, Geoffrey; Lage, C.

doi:10.1109/iedm.2001.979477

Cited by 10 publications

(8 citation statements)

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“…193nm lithography has the advantage of higher linearity and requires fewer enhancement techniques and/or less aggressive MBOPC. 248nm lithography has the advantages of more mature photoresists and significantly lower costs [4]. We have compared the COO of these choices to highlight the large savings which can be realized if aggressive MBOPC will enable the use of lower cost binary mask 248nm lithography for 14 backend patterning layers (7 metal and 7 via).…”

Section: Cost Of Ownership (Coo)mentioning

confidence: 99%

“…We have also evaluated a highly complex 193nm lithography contact patterning process utilizing 9% AttPSM, strong annular illumination, silicon containing bilayer resist [4] and resist reflow. Figure 9 shows the terrific process margins for l3Onm contacts that can be obtained with this combination of methods.…”

Section: Process Complexitymentioning

confidence: 99%

“…We have compared the COO of these choices to highlight the large savings which can be realized if aggressive MBOPC will enable the use of lower cost binary mask 248nm lithography for 14 backend patterning layers (7 metal and 7 via). Using a comprehensive Motorola internal lithography COO model [4] and average values for a range of COO parameters, we estimate the cost savings for the 248nm option to be -16-20% of the total lithographic costs. As lithography is approximately 50%ofthe total wafer processing cost, the enhancement capabilities of MBOPC can be estimated to have a multi-million dollar per year impact upon COO of a leading edge semiconductor manufacturing facility [4].…”

Section: Cost Of Ownership (Coo)mentioning

confidence: 99%

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Model-based design improvements for the 100-nm lithography generation

et al. 2002

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Due to the challenging design rule and CD control requirements of the lOOnm device generation, a large number of complex patterning techniques are likely to be used for random logic devices [ 1] . The complexity of these techniques places considerable strain upon model-based OPC software to identify and compensate for a wide range of printing non-idealities [2]. Additionally, the rapidly increasing cost of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have evaluated the capability of leading edge model-based OPC software to meet the challenging lithography needs of the lOOnm device generation. Specifically, we have implemented and verified model usefulness to correct for pattern deformation in complex binary gate, contact and via processes utilizing highly optimized illumination. Additionally, we present results showing the abilities of model-based methods to accurately find design related printing problems in complementary phase shift gate designs before they are committed to an expensive reticle. ii. IntroductionCurrently in early 2002, leading semiconductor manufacturers are starting pilot-line production of test circuits for the lOOnm technology generation and actively planning development for the 7Onm technology generation. Both of these generations will be accomplished with high numerical aperture (NA) 193nm lithography as the main patterning strategy. The main lithographic challenges of these generations are the lack of linearity (low ki processes); the low depth of focus (DOF) which accompanies high-NA illumination use; the complexity of reticle erthancement technology (RET) or scanner illumination which improves DOF & linearity; and the extremely high cost of ownership (COO) for the leading edge tools necessary to handle these challenges. Other difficult challenges include the relative immaturity of 193nm photoresists, the rising cost (& cycletime) of sophisticated high-end reticles, and the need for complex postprocessing techniques to alter final etched CD values [1,2]. These are difficult problems to overcome before these technologies can be made into working and cost-effective manufacturing processes. The main strategy for overcoming or reducing these problems is the use of optical proximity correction (OPC) methods. The goal of this work is to evaluate the effectiveness of model-based OPC (MBOPC) methods for solving critical patterning problems of the lOOnm technology generation.

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Section: Cost Of Ownership (Coo)mentioning

confidence: 99%

Section: Process Complexitymentioning

confidence: 99%

Section: Cost Of Ownership (Coo)mentioning

confidence: 99%

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Model-based design improvements for the 100-nm lithography generation

et al. 2002

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“…Clearly, controlling the static power dissipation will be a major challenge. From 2003 to 2018, the chip static power One common approach to dealing with this challenge is to fabricate on a chip the highperformance, low V t MOSFET described above as well as other MOSFETs with higher V t and larger EOT to reduce the leakage [7,9,10] (this also enhances the flexibility for system-on-chip [SoC] applications). To illustrate the challenge, Figure 3 presents a plot of the relative chip static power dissipation with scaling, where the normalized dissipation is 1.0 in 2003.…”

Section: Year In Productionmentioning

confidence: 99%

“…Finally, both I sd,leak and τ i from Table 1 are plotted versus calendar year in Figure 2 (τ i is plotted rather than ƒi for convenience in plotting.) One common approach to dealing with this challenge is to fabricate on a chip the highperformance, low V t MOSFET described above as well as other MOSFETs with higher V t and larger EOT to reduce the leakage [7,9,10] (this also enhances the flexibility for system-on-chip [SoC] applications). For high-performance chips, controlling the chip static power dissipation is expected to be increasingly challenging because of the rapid increase in transistor leakage current with scaling noted above.…”

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confidence: 99%

MOSFET Scaling Trends, Challenges, and Key Associated Metrology Issues Through the End of the Roadmap

Zeitzoff¹,

Huff²

2005

AIP Conference Proceedings

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Scalable gate first process for silicon on insulator metal oxide semiconductor field effect transistors with epitaxial high-k dielectrics Abstract. The overall issues and trends in logic MOSFET scaling are discussed from the perspective of the 2003 and 2004 editions of the International Technology Roadmap for Semiconductors. Critical challenges with scaling include managing gate leakage current, polysilicon gate depletion, and short channel effects. Key innovations to address these challenges include high-k gate dielectric, metal gate electrode, strained silicon channel for enhanced mobility, and eventually, non-classical CMOS devices (e.g., FinFETs). These innovations will present significant metrology and characterization challenges as well.

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