Nano and Giga Challenges in Microelectronics 2003
DOI: 10.1016/b978-044451494-3/50001-9
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Integrated Circuit Technologies

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Cited by 8 publications
(2 citation statements)
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“…Recent advancements in semiconductor device technology have led to improved operational performance via physical scaling. [1,2] However, further performance enhancement has been limited by the need to maintain the power consumption per unit area at approximately 100 W cm −2 . To address this challenge, various ultra-low-power logic devices, such as gate-all-around fieldeffect transistors (GAAFETs), steep-switching FETs, and nearthreshold logic devices, have been extensively studied.…”
Section: Introductionmentioning
confidence: 99%
“…Recent advancements in semiconductor device technology have led to improved operational performance via physical scaling. [1,2] However, further performance enhancement has been limited by the need to maintain the power consumption per unit area at approximately 100 W cm −2 . To address this challenge, various ultra-low-power logic devices, such as gate-all-around fieldeffect transistors (GAAFETs), steep-switching FETs, and nearthreshold logic devices, have been extensively studied.…”
Section: Introductionmentioning
confidence: 99%
“…Miniaturization of Si-based complementary metal-oxide semiconductor (CMOS) devices is a continuous challenge in improving device performance, while sustaining the scaling requirements as defined by the Moore's law. 1,2 Due to physical complications, such as gate leakage, 1,3 parasitic resistance/capacitance 1,4 and size channel effects, 1,5,6 further downscaling of CMOS is impeded. Hence, the semiconductor industry is actively searching for potential candidates that can replace Si as the material of choice.…”
mentioning
confidence: 99%