A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations

Hsu, Kai-Ti; Sinha, Subarna; Pi, Yu-Chuan; Ho, Tsung-Yi

doi:10.1109/tcad.2012.2201155

Cited by 3 publications

(2 citation statements)

References 8 publications

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“…Rules need to be updated continuously with feedback from fabrication; otherwise, there is high possibility of over prediction of violations, based on the aggressive range of layout rules generally applied. Several techniques including hierarchy based and using pattern matching approach have been used to improve the efficiency and accuracy of rule‐based layout check [57, 58].…”

Section: Computer‐aided Design (Cad) Analysis For Hotspot Detectionmentioning

confidence: 99%

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

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Optical projection lithography has been the workhorse of the integrate circuit (IC) manufacturing industry to transfer the computer-aided design (CAD) to semiconducting material wafers. The resolution limit of the 193 nm wavelength lithography which was initially targeted for the 90 nm design rule has been further extended to realise ∼10-20 nm devices with ingenious interventions. The three-dimensional fin-shaped field-effect transistor device structure now realise the <20 nm design rule still using 193 nm projection lithography as the widely accepted solution. The extreme ultraviolet wavelength source systems are still in development and testing phases with some recent success reported, but still falling short of supporting volume production requirements. This study reviews the current trends in lithography and the associated resolution enhancement techniques with brief introduction to an integrated CAD analysis for hotspot detection.

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Section: Computer‐aided Design (Cad) Analysis For Hotspot Detectionmentioning

confidence: 99%

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Vikram

Agarwal

2017

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

show abstract

“…Rules need to be updated continuously with feedback from fabrication otherwise there is high possibility of over prediction of violations, based on the aggressive range of layout rules generally applied. Several techniques including hierarchy based and using a pattern matching approach have been used to improve the efficiency and accuracy of rule based layout check [58,59].…”

Section: A Rule Based Hotspot Analysismentioning

confidence: 99%

Critical Review of Current Trends in ASIC Writing and Layout Analysis

Vikram¹,

Agarwal

2016

JSTS:Journal of Semiconductor Technology and Science

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Abstract-Electrical Designs for Application SpecificIntegrated Circuits (ASIC) has undergone a change recently with the advent of the sub-wavelength lithography. The optical projection with 193 nm wavelength has been further extended with the use of immersion and other techniques. The competing trends for printing smaller design features have been discussed in this paper with the discussion of the electrical layout analysis to find unfriendly design features. The early knowledge of the unfriendly design features allows remedial actions in time for better yield on the wafer. There are existing standard design qualification criteria being used in the design and fabrication community, but they seem to be insufficient to guarantee defect free designs. This paper proposes an integrated approach for screening the layout with multiple aspects: layout geometry based, graphical analysis and process model based verification. The results have been discussed with few example design features from the 28nm design layout.

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Performance optimisation of web applications using In-memory caching and asynchronous job queues

Prakash

Kovoor

2016

2016 International Conference on Inventive Computation Technologies (ICICT)

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A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations

Cited by 3 publications

References 8 publications

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Lithography technology for advanced devices and introduction to integrated CAD analysis for hotspot detection

Critical Review of Current Trends in ASIC Writing and Layout Analysis

Performance optimisation of web applications using In-memory caching and asynchronous job queues

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