A Hierarchical Hybrid Optical-Electronic Network-on-Chip

Mo, Kwai Hung; Ye, Yaoyao; Wu, Xiaowen; Zhang, Wei; Liu, Weichen; Xu, Jiang

doi:10.1109/isvlsi.2010.17

Cited by 54 publications

(13 citation statements)

References 15 publications

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“…The network is circuit-switched and some critical network design issues such as path-setup and tear-down are covered in the work. Mo et al [5] proposed a hierarchical mesh-based ONoC. It uses hybrid optical-electronic routers for electronic wormhole switching in local networks and circuit switching in the global mesh-based optical network.…”

Section: Related Workmentioning

confidence: 99%

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

Huang

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Section: Related Workmentioning

confidence: 99%

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

Huang

et al. 2013

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In addition, according to the description above, there are total 192 PSEs in 64-core network, with 384 microresonators. Related literature [5] shows that one 5-port router will need 16 microresonators now. Thus an 8x8 optical mesh network which has 320 5-port routers will use at least 5120 microresonators, which is about 13 times of our architecture.…”

Section: A Optical Loss Analysismentioning

confidence: 99%

“…This paper compares the power consumption of FONoC with a matched electronic NoC and shows the lowpower characteristics of photonic NoC further. A hybrid optical mesh NoC, HOME, is proposed to utilize optical waveguides as well as metallic interconnects in a hierarchical manner [5]. HOME uses wormhole switching for local networks and circuit switching for the global network.…”

Section: Introductionmentioning

confidence: 99%

A Highly Scalable Butterfly-Based Photonic Network-on-Chip

Wang

et al. 2012

2012 IEEE 12th International Conference on Computer and Information Technology

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Future chip multiprocessors will requires low-power, high performance on-chip networks. Photonic interconnects is a promising way to leverage silicon photonics for future CMPs. In this paper, we present a highly scalable BPNoC(butterfly-based photonic NoC). The most important feature of our proposed network is that it can scale to a more large size with acceptable performance by utilizing the characteristics of butterfly topology and basic photonic switching element (PSE2x2). BPNoC is a hierarchical network with an optical sub-network and an electrical sub-network. Optical sub-network with a load-balanced routing algorithm use circuit-based switching to transmit data packets, while the electronic sub-network with improved turnaround algorithm is based on packet-switching for control and data packet transmission. Finally, we analyze the optical loss, power consumption, and network performance for 64-core BPNoC under various synthetic traffic patterns. The results show that our proposed network has much low optical loss, good performance, and high energy efficiency.

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“…The optical network is employed to transfer the payload packets. Since optical buffer technology is still in its infancy, circuit switching has become a practical way to support ONoC, which is applied to various topologies [11]- [13]. Circuit-switched photonic network architectures take advantage of the optical spectrum by establishing a high-bandwidth light path dedicated for data transmission [14].…”

Section: Introductionmentioning

confidence: 99%

New Path-Setup Method for Optical Network-on-Chip

Gao

Wang

et al. 2014

ETRI J

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With high bandwidth, low interference, and low power consumption, optical network-on-chip (ONoC) has emerged as a highly efficient interconnection for the future generation of multicore system on chips. In this paper, we propose a new path-setup method for ONoC to mitigate contentions, such as packets, by recycling the setup packet halfway to the destination. A new, strictly non-blocking 6 × 6 optical router is designed to support the new method. The simulation results show the new path-setup method increases the throughput by 52.03%, 41.94%, and 36.47% under uniform, hotspot-I, and hotspot-II traffic patterns, respectively. The end-to-end delay performance is also improved.

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A Hierarchical Hybrid Optical-Electronic Network-on-Chip

Cited by 54 publications

References 15 publications

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

3-D Mesh-Based Optical Network-on-Chip for Multiprocessor System-on-Chip

A Highly Scalable Butterfly-Based Photonic Network-on-Chip

New Path-Setup Method for Optical Network-on-Chip

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