2005 6th International Conference on ASIC
DOI: 10.1109/icasic.2005.1611255
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A Hardware Efficient VLSI Architecture For FFT Processor in OFDM Systems

Jianming Wu
1
,
Ke Liu
2
,
Bo Shen
3
et al.
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Cited by 5 publications
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Design architecture of generic DFT/DCT 1D and 2D engine controlled by SW instructions

Hassan
1
,
Shalash
2
,
Hamed
3
2010
2010 IEEE Asia Pacific Conference on Circuits and Systems
4
0
7
0
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Design architecture of generic DFT/DCT 1D and 2D engine controlled by SW instructions

Hassan
1
,
Shalash
2
,
Hamed
3
2010
2010 IEEE Asia Pacific Conference on Circuits and Systems
4
0
7
0
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Hardware efficient design of Variable Length FFT Processor

Gautam
1
,
Ray
2
,
Haddow3
2011
14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
11
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13
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Scalable FFT architecture vs. multiple pipeline FFT architectures — Hardware implementation and cost

Suleiman
1
,
Hussein
2
,
Bataineh
3
et al. 2009
2009 IEEE International Conference on Systems, Man and Cybernetics
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