Scalable FFT architecture vs. multiple pipeline FFT architectures &amp;#x2014; Hardware implementation and cost

In this work we introduce Processing Element (PE) scalability in twiddle factor generators for FFT processors. First the twiddle factor indexing scheme for Constant Geometry FFT is analyzed and a CORDIC-based novel algorithm is deduced. It uses single-step rotations and does not need any CORDIC gain correction. Then, two architectures implementing the algorithm are presented with the goal of scalability. The first (shared core) is characterized by both low register count and variable throughput, while the second (pipelined) achieves the maximum throughput during the whole computation. Our hybrid models use both one ROM and multiplier-based CORDIC modules. The designs are then evaluated in terms of register usage and output error, showing scalability of register bits as a function of the number of PEs if compared to other architectures. Architectures were coded in VHDL and synthesized on a Xilinx Virtex-5 330T FPGA

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Scalable hybrid CORDIC-LUT architectures for CG-FFT processors

Congiu

Picciau

Barbaro

et al. 2013

Proceedings of the 2013 9th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)

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Scalable FFT architecture vs. multiple pipeline FFT architectures — Hardware implementation and cost

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Scalable hybrid CORDIC-LUT architectures for CG-FFT processors

Scalable hybrid CORDIC-LUT architectures for CG-FFT processors

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