A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations

He, Yajuan; Zhang, Jiubai; Wu, Xiaoqing; Si, Xin; Zhen, Shaowei; Zhang, Chao

doi:10.1109/tvlsi.2019.2919104

Cited by 54 publications

(49 citation statements)

References 29 publications

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“…This is attributed to an increase in mobility of charge carriers which further increase the write current and improve the write delay. In addition to this, the write access time of LP9T SRAM cell is improved by 1.09×,2.09×,1.63×,2.85×,2.04× as compared to DF8T [21],TG8T [26],PCF10T [18],SPG11T [20] and LP12T [19] SRAM cells respectively. It occurs because of increased write word line voltage which strengthens N2 and N3 transistors.…”

Section: Read/write Access Timementioning

confidence: 97%

“…It happens due to the quadratic relationship between the supply voltage and power dissipation. Further, the read power consumption of LP9T SRAM cell is decreased by 1.41×,1.40×, 1.39×,1.33×,1.38×,1.40× as compared to Conv.6T [28],DF8T [21],TG8T [26],PCF10T [18],SPG11T [20],LP12T [19] SRAM cells respectively. It is because of single sided read structure that minimizes the read bit-line capacitance.…”

Section: Read/write Power Dissipationmentioning

confidence: 99%

“…The write power consumption at different supply voltages has seen in Fig.7 (c). It has indicated that the write power of the LP9T SRAM cell is decreased 2.1×,3.64×, 2.06×,1.96×,4.23×,2.45× as compared to Conv.6T [28],DF8T [21],TG8T [26],PCF10T [18],SPG11T [20],LP12T [19] SRAM cells respectively. This happens due to the weaken of pull-up path through PMOS (P1 and P2) transistors.…”

Section: Read/write Power Dissipationmentioning

confidence: 99%

“…Fig.8(a) shows the time of read access which considered SRAM topologies at various supply voltages value. It is noticed that the LP9T SRAM cell, read access time has been improved by 2.72×,2.5×,3.55×,8.15×,3.49×,5.56× as compared to Conv.6T [28],DF8T [21],TG8T [26],PCF10T [18], SPG11T [20],LP12T [19] SRAM cells respectively. It is attributed to the forward body bias technique in read path which reduces the threshold voltage of N5 transistor which takes minimum time to discharge the read bit-line.…”

Section: Read/write Access Timementioning

confidence: 99%

“…Furthermore, isolated read structure suffer with bit-line leakage current in the read path that increases the read failure probability. Read and write-assist techniques are used in SPG11T SRAM cell as shown in Fig.2(d) [20] for simultaneous improvement in read and write stability. S.Pal et al [21] reported a differential 8T (DF8T) SRAM cell in which read buffer transistors are utilized at pull-down network as shown in Fig.2(e) to expand read noise margin and read current of the cell.…”

Section: Introductionmentioning

confidence: 99%

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A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Kumar¹,

Tomar²

2021

Preprint

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This paper presents a single-ended read and differential write half select free 9T static random access memory (SRAM) cell operates in the sub-threshold region. Proposed 9T SRAM cell shows a reasonable reduction in read and write power dissipation by a factor of 1.41× and 2.1× respectively as of conventional 6T (Conv.6T) SRAM cell. The stacking of transistors at core latch network minimizes the leakage power of the cell. The read static noise margin (RSNM) and write margin (WM) are upgraded by 2.16× and 2.06× respectively as of Conv.6T cell. A forward body bias technique is utilized in read path which results to decreases in read access time by a factor of 2.72× as of standard 6T SRAM cell. The mean value of Ion/Ioff ratio of the proposed cell is improved by 2.92× as compared to the Conv.6T SRAM cell. It is attributed to a reduction in bit-line leakage current. To achieve more soundness in characteristics of the proposed 9T SRAM cell, process variation effect on RSNM, power dissipation, and read current is calculated through Monte Carlo (MC) simulation at 5000 points. The obtained results are compared with reference SRAM cells at 0.3V supply voltage.

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Section: Read/write Access Timementioning

confidence: 97%

Section: Read/write Power Dissipationmentioning

confidence: 99%

Section: Read/write Power Dissipationmentioning

confidence: 99%

Section: Read/write Access Timementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Kumar¹,

Tomar²

2021

Preprint

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Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

Abbasian

Gholipour

Izadinasab

2021

Circuit Theory & Apps

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Graphene nanoribbon and transition metal dichalcogenide field-effect transistors (GNRFETs and TMDFETs) have emerged as favorable candidates to replace conventional metal-oxide-semiconductor (MOS) transistor in future technologies. Their competence must be proven through the study and evaluation of various circuits, including static random access memories (SRAMs). Therefore, this paper presents a single-ended 12T (SE12T) SRAM cell designed using GNRFETs and TMDFETs to evaluate their performance. The proposed SE12T cell designed with GNRFETs/TMDFET device improves read static noise margin by 1.95Â/3.20Â and incurs a penalty of 1.16Â/1.14Â in read delay compared to the GNRFETs/TMDFET-based fully differential 8T cell through a read buffer, decoupling the bitline from the storing nodes during the read operation. Furthermore, two transmission gates (TGs) placed inside the cell core cut off the feedback of cross-coupled inverters pair during the write operation, enhancing write static noise margin by 1.65Â/1.71Â. These two TGs along with high logic level of virtual ground (V GND ) control signal during hold mode reduce leakage power. Existence of a higher number of p-type MOS (PMOS) devices, the presence of stacked transistors, and being single-ended bitcell further reduce this metric, nearly 1.48Â/1.17Â designed with GNRFETs/TMDFET device as compared to FD8T. Furthermore, it is observed from the results that GNRFET-based designs have better performance than those of their TMDFET counterparts. The proposed cell eliminates write half-select disturb, and therefore, bit-interleaving architecture can be applied to reduce multi-bit errors.

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A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications

Abbasian

Gholipour

2022

Circuit Theory & Apps

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The design of power‐efficient SRAM cells is necessary for biomedical applications such as body area networks (BANs) to extent their battery life. SRAM cell's power consists of two main components, including leakage power and dynamic power, in which the former overcomes the latter in advanced technology. This paper presents a low‐leakage single‐bitline 9T (L2SB9T) SRAM cell. The proposed design is free from read‐disturbance issue and eliminates writing “1” problem. The results are carried out by utilizing HSPICE and 16‐nm CMOS PTM at a 0.7 V, 25°C, and under severe PVT variations. The proposed L2SB9T SRAM cell is comprehensively compared with other recently published SRAM cells including conventional 6T, write/read enhanced 8T (WRE8T), transmission‐gate 9T (TG9T), read‐disturb‐free 9T (RDF9T), fully differential 10T (Chang10T), data‐independent read port 10T (DIRP10T), and single‐bitline 11T (SB11T). It shows at least 1.26X/1.07X/1.01X improvement in read static noise margin (RSNM)/write static noise margin (WSNM)/write margin (WM). Furthermore, the leakage power is reduced by the proposed cell, at least 1.137X. Moreover, the suggested cell consumes the third/second best dynamic read/write power, which is 1.42X/1.37X lower than that of conventional 6T SRAM cell. The proposed L2SB9T SRAM cell performs its read/write operation reliably by showing at least 1.71X narrower speared in RSNM compared to the best SRAM cell and third best WM variability. For all these improvements, the proposed L2SB9T SRAM cell incurs a 4.20X/1.06X/1.808X penalty in read delay/write delay/layout area when compared with the best SRAM cells, that is, the Chang10T/6T/6T.

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A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write/Read-Assist Scheme for Ultralow-Voltage Operations

Cited by 54 publications

References 29 publications

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design

A low‐leakage single‐bitline 9T SRAM cell with read‐disturbance removal and high writability for low‐power biomedical applications

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