A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure

Arjomand, Mohammad; Boroumand, Amirali; Sarbazi-Azad, Hamid

doi:10.1016/j.compeleceng.2013.11.031

Cited by 6 publications

(3 citation statements)

References 31 publications

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“…However, the main reason to implement switches as small MoT is fairness, as 2D mesh operating frequency will be similar to the operating frequency of the MoT tree. Network performance can be measured with FPGA-based prototyping [24] or with cycle accurate network simulators. In this paper we have used a cycle accurate simulator as it provides more flexibility to model each network configuration.…”

Section: Resultsmentioning

confidence: 99%

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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Manycore CMP systems are expected to grow to tens or even hundreds of cores. In this paper we show that the effective co-design of both, the networkon-chip and the coherence protocol, improves performance and power meanwhile total area resources remain bounded. We propose a snoopy-aware network-onchip topology made of two mesh-of-tree topologies. Reducing the complexity of the coherence protocol -and hence its resources -, and moving this complexity to the network, leads to a global decrease in power consumption meanwhile area is barely affected. Benefits of our proposal are due to the high-throughput and low delay of the network, but also due to the simplicity of the coherence protocol. The proposed network and protocol minimizes communication amongst cores when compared to traditional solutions based either on 2D-mesh topologies or in directory-based protocols.

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Section: Resultsmentioning

confidence: 99%

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Roca

Hernández

Lodde

et al. 2015

Computers & Electrical Engineering

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“…These technologies pose formidable physical design challenges for long wires and global on-chip connections. Therefore, several designers have proposed to change from the fully synchronous design paradigm to the Globally Asynchronous, Locally Synchronous (GALS) design paradigm [1,2] enabling to split the application into synchronous domains, placing each domain inside a limited region called tile.…”

Section: Introductionmentioning

confidence: 99%

Models of computation for NoC mapping: Timing and energy saving awareness

Marcon

Webber

Susin

2017

Microelectronics Journal

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“…Bus-based architectures are simple and completely widespread; use of these approaches do not scale very well when more intellectual property (IP) cores are integrated in a system and will not meet the requirements of the future MPSoCs because of their seriously limited scalability. Also, they quickly become the bottleneck of a system [2]- [4]. By using the interconnection network as the communication infrastructure between cores, Networks-on-Chip (NoCs) are emerging as an efficient and scalable alternative to existing on-chip interconnects which allow systems to be designed modularly.…”

Section: Introductionmentioning

confidence: 99%

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

Salem¹,

Salah²,

Bennour³

et al. 2017

ijacsa

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Abstract-Chip communication architectures become an important element that is critical to control when designing a complex MultiProcessor System-on-Chip (MPSoC). This led to the emergence of new interconnection architectures, like Network-on-Chip (NoC). NoCs have been proven to be a promising solution to the concerns of MPSoCs in terms of data parallelism. Field-Programmable Gate Arrays (FPGA) has some perceived challenges. Overcoming those challenges with the right prototyping solutions is easy and cost-effective leading to much faster time-to-market. In this paper, we present an FPGA based on rapid prototyping in hardware/software co-design and design evaluation of a mixed HW/SW MPSoC using a NoC. A case study of two-dimensional mesh NoC-based MPSoC architecture is presented with a validation environment. The synthesis and implementation results of the NoC-based MPSoC on a Virtex 5 ML 507 enable a reasonable frequency (151.5 MHz) and a resource usage rate equals to 58% (6,586 out of 11,200 slices used).

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A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure

Cited by 6 publications

References 31 publications

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems

Models of computation for NoC mapping: Timing and energy saving awareness

FPGA Prototyping and Design Evaluation of a NoC-Based MPSoC

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