A gallium nitride fet based DC-DC converter for the new 48 V automotive system

Roschatt, Philipp Marc; McMahon, R.A.; Pickering, Stephen

doi:10.1049/cp.2014.0507

Cited by 8 publications

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“…Equation ( 5) is obtained by substituting ( 3) and ( 4) into ( 1) and ( 2) and applying the Laplace transform. Thus, Isame can be expressed as in (6). Finally, the sum of the currents flowing through the two conductors, Itotal, is expressed as shown in (7), based on the relationship between ( 4) and ( 6).…”

Section: A Theoretical Analysis Of Parasitic Inductancementioning

confidence: 99%

“…Therefore, research on wide-bandgap (WBG) devices, which have superior physical properties more than Si, has been conducted, and as a result, new power semiconductor devices are being developed and mass-produced. Recently, gallium nitride high electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs have emerged as WBG devices, enabling the revolutionary development of power conversion systems with higher efficiency and power density [2]- [6]. Especially, GaN HEMTs have faster switching speed and lower conduction loss than SiC MOSFET owing to the high electron density forming a twodimensional electron gas (2DEG) layer [7].…”

Section: Introductionmentioning

confidence: 99%

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Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter

et al. 2022

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Among the wide-bandgap devices, gallium nitride high electron mobility transistors (GaN HEMTs) are contributing to the high power density technology of power conversion systems due to their excellent physical properties. In contrast, the driving voltage and threshold voltage are relatively low compared to conventional power semiconductor devices, so a reliable circuit design is required. In this paper, a parasitic inductance reduction design method for the stable driving of GaN HEMTs is proposed. To reduce parasitic inductance, we propose a vertical lattice loop structure having multiple loops, and this method can be applied regardless of the package type and shape of GaN HEMT. For the design of the proposed vertical lattice loop structure, the reference loop is defined to minimize leakage inductance and the identical loop is vertically stacked. The proposed structure is applied 6-layer PCB design example and verified by experimental results. Furthermore, the proposed design method is applied at the buck converter, and improved efficiency is verified from 600 kHz to 1MHz switching frequency.

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Section: A Theoretical Analysis Of Parasitic Inductancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter

et al. 2022

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Optimizing PWM Control for Efficiency and Reduction of False Turn-On Events in Synchronous Buck GaN Converters

Kashyap

Bauman

2021

IEEE Access

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Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

Roschatt

McMahon

Pickering

2015

2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia)

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The low threshold voltage of Gallium Nitride enhancement mode FETs is a concern in high current high frequency synchronous DC-DC buck converters. Applying a negative gate voltage to the low side FET to improve the dV/dt robustness increases the voltage drop between source and drain during dead-time conduction. This has consequences not only on the efficiency, but more importantly on the bootstrap voltage. Even with precise dead-timing, the large voltage drop from drain to source still results in a significant variation of the bootstrap voltage. This results in a change of gate turn on speed and increases the dV/dt stress. The very short dead-time needed to avoid great variations in the bootstrap voltage means that the voltage drop from source to drain can no longer bet treated as a constant as it varies greatly during the dead-time.

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A gallium nitride fet based DC-DC converter for the new 48 V automotive system

Cited by 8 publications

References 0 publications

Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter

Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter

Optimizing PWM Control for Efficiency and Reduction of False Turn-On Events in Synchronous Buck GaN Converters

Investigation of dead-time behaviour in GaN DC-DC buck converter with a negative gate voltage

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