Design Method of Vertical Lattice Loop Structure for Parasitic Inductance Reduction in a GaN HEMTs-Based Converter

Abstract

Among the wide-bandgap devices, gallium nitride high electron mobility transistors (GaN HEMTs) are contributing to the high power density technology of power conversion systems due to their excellent physical properties. In contrast, the driving voltage and threshold voltage are relatively low compared to conventional power semiconductor devices, so a reliable circuit design is required. In this paper, a parasitic inductance reduction design method for the stable driving of GaN HEMTs is proposed. To reduce parasitic inductance, we propose a vertical lattice loop structure having multiple loops, and this method can be applied regardless of the package type and shape of GaN HEMT. For the design of the proposed vertical lattice loop structure, the reference loop is defined to minimize leakage inductance and the identical loop is vertically stacked. The proposed structure is applied 6-layer PCB design example and verified by experimental results. Furthermore, the proposed design method is applied at the buck converter, and improved efficiency is verified from 600 kHz to 1MHz switching frequency.

Three-Dimensional Lattice Structure to Reduce Parasitic Inductance for WBG Power Semiconductor-Based Converters

“…Accordingly, parasitic inductance reduction methods that use magnetic flux cancellation between adjacent conductors, which can be applied in the general case, have been studied [15][16][17][18][19][20][21]. In [15][16][17], structures can reduce parasitic inductance through single current loop-based magnetic flux cancellation.…”

“…In [18][19][20][21], multiple current loop-based inductance reduction methods were proposed to improve flux cancellation. In [18], a switching package capable of constructing multiple current loops in a single layer was proposed.…”

“…However, this is only applicable to certain package types of devices that can form multiple current loops. In [19][20][21], more general multiple loop-based methods were proposed. Dechant et al [19] and Hammer et al [20] proposed structures that can improve the magnetic flux cancellation in multiple current loops without the limitation of package type.…”

“…However, these articles only presented a conceptual method and did not provide a quantitative interpretation of the improvement of inductance reduction by a multi-loop structure, nor did they provide a detailed design process based on it. Yang et al [21] completed the foundation of a multi-loop-based inductance reduction method by providing a detailed principle of inductance reduction by a multi-loop structure and its design method. However, the above methods [19][20][21] did not fully utilize the inductance reduction effect of multi-loop structures because they only considered magnetic flux offset between layers, without considering the layers themselves.…”

“…Yang et al [21] completed the foundation of a multi-loop-based inductance reduction method by providing a detailed principle of inductance reduction by a multi-loop structure and its design method. However, the above methods [19][20][21] did not fully utilize the inductance reduction effect of multi-loop structures because they only considered magnetic flux offset between layers, without considering the layers themselves. In this study, a three-dimensional (3-D) lattice structure that can cancel the magnetic flux between the layers and in a single layer is proposed to further reduce parasitic inductance.…”