A functional 0.69 μm/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

Arnaud, F.; Bœuf, F.; Salvetti, F.; Lenoble, D.; Wacquant, F.; Regnier, C.; Morin, Pauline; Emonet, N.; Denis, E.; Oberlin, Jean-Claude; Ceccarelli, Daniele; Vannier, P.; Imbert, Guy; Sicard, A.; Perrot, C.; Belmont, O.; Guilmeau, I.; Sassoulas, Pierre-Olivier; Delmedico, S.; Palla, R.; Leverd, F.; Beverina, A.; DeJonghe, V.; Broekaart, M.; Pain, Laurent; Todeschini, J.; Charpin, Murielle; Laplanche, Y.; Neira, Diego Andres Galvis; Vachellerie, V.; Borot, B.; Devoivre, T.; Bicais, N.; Hinschberger, B.; Pantel, R.; Revil, N.; Parthasarathy, C.; Planes, N.; Brut, H.; Farkas, J.; Uginet, J.; Stolk, P. A.; Woo, M.

doi:10.1109/vlsit.2003.1221088

Cited by 21 publications

(18 citation statements)

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“…The cannel width of the cell is 0.12um and the gate length is 0.18um, allowing the aggressive static electrical performances re- The first thing that has to be proven is that the inclusion of the Flash and HV MOS portion of the flow is not modifying the LV CMOS performances. This can be seen in Fig.3, where the minimum power supply to obtain functionality on 2Mbit SRAM cuts is reported for two 0.67μm 2 cuts [9]. The two cuts are using cells with different threshold voltages.…”

Section: Process Flow and Architecturementioning

confidence: 92%

High performance Flash memory for 65 nm embedded automotive application

Piazza

Boccaccio

Bruyère

et al. 2010

2010 IEEE International Memory Workshop

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IntroductionSystem on a chip appears to be, since years, one of the major catchwords of the semiconductor industry, implying the capability to integrate different functions on the same silicon. To this purpose, the integration of high performance logic and Flash memory, which presents several advantages, such as larger system flexibility and reduction of power dissipation, appears very attractive [1]. However, the introduction in the market of a new generation of products with flash memories on board has always been hampered by the technological complexity related to the contrast of the natural evolution of advanced CMOS technological process, which leads to the operative voltage reduction and the con-

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Section: Process Flow and Architecturementioning

confidence: 92%

High performance Flash memory for 65 nm embedded automotive application

Piazza

Boccaccio

Bruyère

et al. 2010

2010 IEEE International Memory Workshop

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“…5. Since the layout guidelines for the 45nm technology was not available to us, we have used the layout guidelines presented in [15] which are a scaled version of the 90nm technology. They could also be obtained by scaling the sizes and dimensions given in [16].…”

Section: Areamentioning

confidence: 99%

Design and Analysis of Two Low-Power SRAM Cell Structures

Razavipour

Afzali-Kusha

Pedram

2009

IEEE Trans. VLSI Syst.

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Abstract-In this paper, two Static Random Access Memory (SRAM) cells that reduce the static power dissipation due to gate and sub-threshold leakage currents are presented. The first cell structure results in reduced gate voltages for the NMOS pass transistors, and thus lowers the gate leakage current. It reduces the subthreshold leakage current by increasing the ground level during the idle (inactive) mode. The second cell structure makes use of PMOS pass transistors to lower the gate leakage current. In addition, dual threshold voltage technology with forward body biasing is utilized with this structure to reduce the subthreshold leakage while maintaining performance. Compared to a conventional SRAM cell, the first cell structure decreases the total gate leakage current by 66% and the idle power by 58% and increases the access time by approximately 2% while the second cell structure reduces the total gate leakage current by 27% and the idle power by 37% with no access time degradation.

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“…VTCs for 90nm and 65nm technology nodes have been obtained using Berkeley Predictive Technology Model (BPTM) [4] and may give overly optimistic SNM values. SNM of only 95mV has been reported for 65nm technology [5], which is over four times less than for 180nm technology, while the supply voltage has been scaled down less than twice.…”

Section: Sram Stability Faultsmentioning

confidence: 94%

“…Open in contact "2" or "3" on the left-hand and right-hand sides of the cell respectively corresponds to a resistive connection of Q3 or Q4 drains to nodes A or B respectively ( Figure 8) and represents an asymmetric defect [9]. As the technology is moving towards the smaller feature sizes, the "split word line" cell layouts have been adopted by the foundries [5,8]. They have separate source contacts for each of the load PMOS devices thus increasing the total number of possible locations of open contacts which can cause DRFs or SFs to four.…”

Section: Resistive Opensmentioning

confidence: 99%

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Word line pulsing technique for stability fault detection in sram cells

Pavlov

Azimane

Gyvez

et al.

IEEE International Conference on Test, 2005.

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Pavlov, A.; Azimane, M.; Pineda de Gyvez, J.; Sachdev, M. Please check the document version of this publication:• A submitted manuscript is the author's version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website.• The final author version and the galley proof are versions of the publication after peer review.• The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rightsCopyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights.• Users may download and print one copy of any publication from the public portal for the purpose of private study or research.• You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal ? Take down policyIf you believe that this document breaches copyright please contact us providing details, and we will remove access to the work immediately and investigate your claim.

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A functional 0.69 μm/sup 2/ embedded 6T-SRAM bit cell for 65 nm CMOS platform

Cited by 21 publications

References 0 publications

High performance Flash memory for 65 nm embedded automotive application

High performance Flash memory for 65 nm embedded automotive application

Design and Analysis of Two Low-Power SRAM Cell Structures

Word line pulsing technique for stability fault detection in sram cells

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