Word line pulsing technique for stability fault detection in sram cells

Pavlov, A.; Azimane, Mohamed; Gyvez, José Pineda de; Sachdev, Manoj

doi:10.1109/test.2005.1584045

Cited by 16 publications

(14 citation statements)

References 14 publications

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“…Figure 1: 6T SRAM core-cell Moreover, it has been shown in [5] that resistive bridges and threshold voltage mismatches, which are more and more likely to occur in VDSM technologies using very aggressive design rules, may also be the root cause of stability faults.…”

Section: Rdfmentioning

confidence: 99%

“…Programmable stability fault detection has been described in [4,5,6]. These DfT techniques consist in using one or more core-cells per column to modulate the bit line voltage levels.…”

Section: B State-of-the-artmentioning

confidence: 99%

“…These DfT techniques consist in using one or more core-cells per column to modulate the bit line voltage levels. In [5], the authors present the Word Line Pulsing Technique (WLPT). It consists in applying multiple read operations on a core-cell (without precharge) to reduce the level on the bit line 'BL' (if the core-cell stores a logic '0') or on the complementary bit line 'BLB' (if the core-cell stores a logic '1').…”

Section: B State-of-the-artmentioning

confidence: 99%

“…On the other hand, when the weak write stress is programmable, the test quality versus test yield tradeoff can be adjusted without design interactions and can be based only on the results of the post-silicon testing. Programmable threshold methods have been described in [4,5,6]. These DfT techniques consist in using the content of one or more core-cells in the column of the core-cell under test to modulate the bit line voltage levels and then use these levels to perform a weak write stress.…”

Section: Introductionmentioning

confidence: 99%

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A new design-for-test technique for SRAM core-cell stability faults

Ney¹,

Dilillo²,

Girard³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Core-cell stability represents the ability of the core-cell to keep the stored data. With the rapid development of semiconductor memories, their test is becoming a major concern in VDSM technologies. It provides information about the SRAM design reliability, and its effectiveness is therefore mandatory for safety applications. Existing core-cell stability Design-for-Test (DfT) techniques consist in controlling the voltage levels of bit lines to apply a weak write stress on the core-cell under test. If the core-cell is weak, the weak write stress induces the faulty swap of the core-cell. However, these solutions are costly in terms of area and test application time, and generally require modifications of critical parts of the SRAM (core-cell array and/or the structure generating the internal auto-timing). In this paper, we present a new DfT technique for stability fault detection. It consists in modulating the word line activation in order to perform an adjustable weak write stress on the targeted core-cell for stability fault detection. Compared to existing DfT solutions, the proposed technique offers many advantages: programmability, low area overhead, low test application time. Moreover, it does not require any modification of critical parts of the SRAM.

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Section: Rdfmentioning

confidence: 99%

“…Programmable stability fault detection has been described in [4,5,6]. These DfT techniques consist in using one or more core-cells per column to modulate the bit line voltage levels.…”

Section: B State-of-the-artmentioning

confidence: 99%

Section: B State-of-the-artmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

A new design-for-test technique for SRAM core-cell stability faults

Ney¹,

Dilillo²,

Girard³

et al. 2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

“…Defects in a gate/cell, such as resistive open/short or resistive leakage, will show complicated aspects [1,13,14]. A transistor level simulation is used as "defect activation" for accurate estimation of defective voltage.…”

Section: Intra-cell Defectmentioning

confidence: 99%

Defect Diagnosis - Reasoning Methodology

Satô¹,

Sugiura²,

Shimoda³

et al. 2006

2006 15th Asian Test Symposium

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Diagnosis has become a crucial technology for early debugging and yield improvement. However, the conventional diagnosis methods are not good at locating the defects that are not precisely expressed only with logical fault models. In this paper, we propose a novel defect diagnosis methodology, which is based on the evaluation of defect behaviors using physical information. We examine suspected nodes' voltages by comparing with the observed responses of ATE. In the examination, we use "defect activation", which is an estimation method of defective nodes' voltages using physical information. Using this methodology, we introduce examples of diagnosis for open defects in a cell, and for interconnect open defects. Those successful results show the effectiveness of the defect diagnosis.

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