A fully-integrated highly linear zero-IF CMOS cellular CDMA receiver

Aparin, V.; Kim, Nam-Soo; Brown, Gerald W.; Wu, Yue; Cicalini, A.; Kwok, S.K.; Persico, C.

doi:10.1109/isscc.2005.1494000

Cited by 23 publications

(8 citation statements)

References 5 publications

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“…Due to that, key issues are Tx leaking into the Rx, a demanding VCO phase noise of 139 dBc/Hz at 900 kHz due to the degradation of the wanted signal by reciprocal mixing, and intermodulation of high level blockers [14]. With these requirements the amplification is split commonly into a LNA1 and LNA2 design that necessitates an IIP3 of 8 dBm and 9 dBm, respectively [15].…”

Section: B Cdma2000 and 1xevdvmentioning

confidence: 99%

Multi-Mode Receiver Design for Wireless Terminals

Hueber¹,

Stuhlberger

Holm

et al. 2007

2007 European Conference on Wireless Technologies

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The ongoing evolution from 2G to 3G and beyond confronts the cellular market with the challenges of a broad diversity of communication standards. Furthermore, increasing levels of integration with minimum external component count, advances in semiconductor process technology, and the requirement for multi-mode operation are pivotal demands of the RF-IC manufactures to achieve fast design cycles and low product cost. As a result, reconfiguration of the wireless terminal has become the key issue in the design of wireless terminals. This paper discusses the requirements for multi-mode reconfigurable wireless receivers with focus put onto mixed-signal and digital enhancements to traditional analog front-end designs. The flexibility a digitalfront-end (DFE) introduces is studied with respect to the main cellular communication standards (GSM/EDGE, CDMA2000, W-CDMA/HSDPA, and LTE) and satellite navigation systems (GPS, Galileo), with considerations of impacts on the capability of an implementation of a software-defined-radio (SDR).

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Section: B Cdma2000 and 1xevdvmentioning

confidence: 99%

Multi-Mode Receiver Design for Wireless Terminals

Hueber¹,

Stuhlberger

Holm

et al. 2007

2007 European Conference on Wireless Technologies

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“…The upper limit of the resistor value was set by linearity and voltage gain of the circuits. The feedback capacitors are large in order to attenuate the out-of band blockers [7]. Although using big feedback capacitors creates a low-frequency gain roll-off at the IF output, this can be characterized and corrected in later stages as long the noise figure is low and the gain is high enough for the IF frequency of interests.…”

Section: Op-amp and The Feedback Loadmentioning

confidence: 99%

A 1.5V 0.7-2.5GHz CMOS Quadrature Demodulator for Multi-Band Direct-Conversion Receivers

Poobuapheun

Chen

Boos

et al. 2006

IEEE Custom Integrated Circuits Conference 2006

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This paper presents an integrated quadrature demodulator with on-chip frequency divider implemented in a 0.13 µm CMOS technology. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. From 700MHz to 2.5GHz, the demodulator achieves 10dB DSB NF with 9-33 kHz 1/f-noise corner and 35dB of low frequency voltage gain. The total chip draws 20mA-24mA from a single 1.5V supply.

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“…MOSFET performance is more than sufficient for commercial wireless applications [1,2]. The most significant challenge is bringing products to market on a competitive schedule.…”

Section: Introductionmentioning

confidence: 99%