A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

Kok-Siang, Tan; Sulaiman, M.S.; Reaz, Mamun Bin Ibne; Hean-Teik, Chuah; Sachdev, Manoj

doi:10.1007/s10470-007-9062-8

Cited by 3 publications

(1 citation statement)

References 10 publications

(15 reference statements)

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“…PLLs based are often implemented in designing CDR because they offer filtering to the phase or frequency signal. With transfer rate of 5 Gbps, PLL approached are preferably chosen in [5] and [6].…”

Section: Introductionmentioning

confidence: 99%

Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)

Ashari¹,

Nordin²

2012

IIUMEJ

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Modern communication and computer systems require rapid (Gbps), efficient and large bandwidth data transfers. Agressive scaling of digital integrated systems allow buses and communication controller circuits to be integrated with the microprocessor on the same chip. The Peripheral Component Interconnect Express (PCIe) protocol handles all communcation between the central processing unit (CPU) and hardware devices. PCIe buses require efficient clock data recovery circuits (CDR) to recover clock signals embedded in data during transmission. This paper describes the theoretical modeling and simulation of a phase-locked loop (PLL) used in a CDR circuit. A simple PLL architecture for a 5 GHz CDR circuit is proposed and elaborated in this work. Simulations were carried out using a Hardware Description Language, Verilog-AMS. The effect of jitter on the proposed design is also simulated and evaluated in this work. It was found that the proposed design is robust against both input and VCO jitter.ABSTRAK: Sistem komunikasi dan komputer moden memerlukan pemindahan data yang cekap (Gbps), dan bandwidth yang besar. Pengecilan agresif menggunakan teknik sistem digital bersepadu membenarkan bas dan litar pengawal komunikasi disatukan dengan mikroprocessor dalam cip yang sama. Protokol persisian komponen sambung tara ekspres (PCIe) mengendalikan semua komunikasi antara unit pemprosesan pusat (CPU) dan peranti perkakasan. Bas PCIe memerlukan litar jam pemulihan data (CDR) yang cekap untuk mendapatkan kembali isyarat jam yang tertanam dalam data semasa transmisi. Karya ini menerangkan teori pemodelan dan simulasi gelung fasa terkunci (PLL) untuk CDR. Rekabentuk 5 GHz PLL yang mudah telah dicadangkan dalm kertas kerja ini. Simulasi telah dijalankan menggunakan perisian verilog-AMS. Simulasi mengunnakan kesan ketar dalam reka bentuk yang dicadangkan telah dinilai. Reka bentuk yang dicadangkan terbukti teguh mengatasi ganguan ketar di input dan VCO.KEY WORDS: phase-locked loop (PLL); jitter; phase detector; low-pass filter; voltage-controlled oscillator

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Section: Introductionmentioning

confidence: 99%

Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)

Ashari¹,

Nordin²

2012

IIUMEJ

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Receiver Front-End for 1.25-Gb/s SI-POF

Gasca

Pueyo

Aldea

2014

Analog Circuits and Signal Processing

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Design of a 5GHz phase-locked loop

Ashari

Nordin

Ibrahimy

2011

2011 IEEE Regional Symposium on Micro and Nano Electronics

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Noise or jitter performance is a major concern in the design of phase-locked loop (PLL). Linearity and speed issues are of relevance when receiving data at gigahertz speed. The main function of a PLL circuit is to generate stable higher frequencies (GHz) output from a lower input frequency signal. PLLs are often used in communication technology to implement a variety of functions such as clock recovery, frequency multiplication, and clock synchronization. This paper presents the design and simulation results of PLL with low jitter performance. The key goal is to design and develop an analog PLL circuit for 5 GHz clock data recovery circuit. The PLL comprises of a phase frequency detector (PFD), low pass filter, voltage controlled oscillator (VCO), and feedback divider. In this work, analog mixed-signal architecture of PLL is simulated using hardware discipline modeling language, Verilog-AMS HDL. Multilingual and Mixed-Signal simulator SMASH software has been used for the Verilog-AMS design. A 5 GHz PLL with less jitter was successfully designed in this work.

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A fully-integrated 5 Gbit/s CMOS clock and data recovery circuit

Cited by 3 publications

References 10 publications

Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)

Theoretical Modeling and Simulation of Phase-Locked Loop (PLL) for Clock Data Recovery (CDR)

Receiver Front-End for 1.25-Gb/s SI-POF

Design of a 5GHz phase-locked loop

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