A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs

Biondi, Alessandro; Balsini, Alessio; Pagani, Marco; Rossi, Enrico; Marinoni, Mauro; Buttazzo, Giorgio

doi:10.1109/rtss.2016.010

Cited by 56 publications

(46 citation statements)

References 19 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Refer to [8] for a complete review of self-suspending tasks theory and an explanation of the existing misconceptions. Finally, in [7] authors design a framework to support real-time systems on FPGAs and provide a response time analysis to verify the schedulability of a set of tasks with software parts and hardware accelerated functions.…”

Section: Related Workmentioning

confidence: 99%

Response-Time Analysis of DAG Tasks Supporting Heterogeneous Computing

Serrano¹,

Quiñones²

2018

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

View full text Add to dashboard Cite

Hardware platforms are evolving towards parallel and heterogeneous architectures to overcome the increasing necessity of more performance in the real-time domain. Parallel programming models are fundamental to exploit the performance capabilities of these architectures. This paper proposes a novel response time analysis (RTA) for verifying the schedulability of DAG tasks supporting heterogeneous computing. It analyzes the impact of executing part of the DAG in the accelerator device. As a result, the response time upper bound of the system is more precise than the one provided by currently existing RTA targeting homogeneous architectures. INTRODUCTIONParallel and heterogeneous hardware architectures become mainstream in the embedded domain to cope the increasing performance requirements. These architectures integrate low power generalpurpose multi-cores (known as host) with dedicated accelerator devices like DSP fabrics, GPUs or FPGAs. Some examples are the NVIDIA Tegra X1 [14], TI Keystone II [20] or Xilinx UltraScale [11].Parallel programming models are fundamental to effectively exploit the huge performance capabilities of these architectures. As an example, OpenMP [15] is increasingly being adopted in architectures targeting embedded systems. As a matter of fact, all parallel architectures presented above support OpenMP in their software development kit. Moreover, OpenMP incorporates a host-centric acceleration model to efficiently offload code and data to devices.Functional and non-functional verification is fundamental when designing real-time embedded systems. However, the use of parallel programming models like OpenMP involves many challenges to assure that software satisfies both functional and non-functional requirements. This paper addresses the latter, focusing on the worstcase response time analysis of OpenMP programs. It is worth mentioning however that recent works have addressed functional verification of OpenMP programs [16], demonstrating the benefits of using OpenMP in real-time embedded systems.Regarding timing verification, the sporadic DAG task model [6] analyzes the response time of systems composed of parallel tasks modeled with direct acyclic graphs (DAGs) [4,9,12]. Interestingly,

show abstract

Section: Related Workmentioning

confidence: 99%

Response-Time Analysis of DAG Tasks Supporting Heterogeneous Computing

Serrano¹,

Quiñones²

2018

2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC)

View full text Add to dashboard Cite

show abstract

“…Tasks can self-suspend their execution, e.g., due to I/O operations or to use hardware accelerators [11]. The total suspension time a job of τ i is upper-bounded by S i .…”

Section: System Modelmentioning

confidence: 99%

The SRP Resource Sharing Protocol for Self-Suspending Tasks

Nelissen

Biondi

2018

2018 IEEE Real-Time Systems Symposium (RTSS)

Self Cite

View full text Add to dashboard Cite

Motivated by the increasingly wide adoption of realtimeworkload with self-suspending behaviors, and the relevanceof mechanisms to handle mutually-exclusive shared resources, thispaper takes a new look at locking protocols for self-suspendingtasks under uniprocessor fixed-priority scheduling. Pitfalls whenintegrating the widelyadopted Stack Resource Policy (SRP) withself-suspending tasks are firstly illustrated, and then a new fine grainedSRP analysis is presented. Next, a new locking protocol,named SRP-SS, is proposed to overcome the limitations of theoriginal SRP. The SRP-SS is a generalization of the SRP to copewith the specificities of selfsuspending tasks. It therefore reducesto the SRP under some configurations and hence theoreticallydominates the SRP. It also ensures backward compatibility forapplications developed specifically for the SRP. The SRP-SScomes with its own schedulability analysis and configurationalgorithm. The performances of the SRP and SRP-SS are finallystudied by means of schedulability experiments.

show abstract

“…The work presented in [8] proposes a software framework that exploits HwAs combined with DPR in the development of safety-critical real-time systems. It presents a model used to derive the response-time analysis to verify the schedulability of a real-time task set under given constraints and assumptions.…”

Section: Related Workmentioning

confidence: 99%

Can real-time systems benefit from dynamic partial reconfiguration?

Pezzarossa

Kristensen

Schoeberl

et al. 2017

2017 IEEE Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium of System-on-Chip (SoC)

View full text Add to dashboard Cite

Abstract-In real-time systems, a solution where hardware accelerators are used to implement computationally intensive tasks can be easier to analyze, in terms of worst-case execution time (WCET), than a pure software solution. However, when using FPGAs, the amount and the complexity of the hardware accelerators are limited by the resources available. Dynamic partial reconfiguration (DPR) of FPGAs can be used to overcome this limitation by replacing the accelerators that are only required for limited amounts of time with new ones. This paper investigates the potential benefits of using DPR to implement hardware accelerators in real-time systems and presents an experimental analysis of the trade-offs between hardware utilization and WCET increase due to the reconfiguration time overhead of DPR. We also investigate the trade-off between the use of multiple specialized accelerators combined with DPR instead of the use of a more general accelerator. The results show that, for computationally intensive tasks, the use of DPR can lead to a more efficient use of the FPGA, while maintaining comparable computational performance.

show abstract

A Framework for Supporting Real-Time Applications on Dynamic Reconfigurable FPGAs

Cited by 56 publications

References 19 publications

Response-Time Analysis of DAG Tasks Supporting Heterogeneous Computing

Response-Time Analysis of DAG Tasks Supporting Heterogeneous Computing

The SRP Resource Sharing Protocol for Self-Suspending Tasks

Can real-time systems benefit from dynamic partial reconfiguration?

Contact Info

Product

Resources

About