A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization

Xue, Jiying; Deng, Yangdong; Ye, Zuochang; Wang, Hongrui; Liu, Yang

doi:10.1109/tvlsi.2010.2102374

Cited by 19 publications

(10 citation statements)

References 25 publications

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“…In theory, it may be possible to precharacterize the stress by parameterizing the layout of the neighbors of a cell, but the number of cases to be characterized for all possible neighbors can be large. In the published literature [1], [2], the only known accurate method involves computationally expensive finite element simulation for each transistor, which is impractical for layouts of realistic-sized circuits.…”

Section: Introductionmentioning

confidence: 99%

“…Much of the literature in this area [3]- [6] is based entirely on the use of one-dimensional models that account for stress components only along the longitudinal direction (i.e., along the channel direction). However, finite element simulations in [1], [2] show that STI stress in the transverse direction, perpendicular to the channel direction, also impacts the circuit performance. Furthermore, [3]- [6] use only a single component of the stress tensor for performance evaluation, while the entire stress tensor must be evaluated to accurately analyze STI-induced circuit performance variation.…”

Section: Introductionmentioning

confidence: 99%

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The impact of shallow trench isolation effects on circuit performance

Marella

Sapatnekar

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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Abstract-In nanometer technologies, shallow trench isolation (STI) induces thermal residual stress in active silicon due to post-manufacturing thermal mismatch. The amount of STI around an active region depends on the layout of the design, and the biaxial stress due to STI results in placement-dependent variations in the the transistor mobilities and threshold voltages of the active devices. An analytical model based on inclusion theory in micromechanics is employed to accurately estimate the stresses and the strains induced in the active region by the surrounding STI in the layout. The induced changes in mobility and threshold voltage changes are computed at the transistor level, and then propagated to the gate and circuit levels to predict circuit-level delay and leakage power for a given placement.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

The impact of shallow trench isolation effects on circuit performance

Marella

Sapatnekar

2013

2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…Then, several stress modelling techniques were developed by [16,18,20]. Recently, LDE-aware circuit design methodologies were proposed by [3,21]. Researchers analyzed and modelled the LDEs on circuits and gave design and layout guidelines to mitigate the influence of LDEs and improve circuit performance.…”

Section: Introductionmentioning

confidence: 99%

Layout-dependent-effects-aware analytical analog placement

Tseng

Liu

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Layout-dependent effects (LDEs) have become a critical issue in modern analog and mixed-signal circuit designs. The three major sources of LDEs, well proximity, length of oxide diffusion, and oxide-to-oxide spacing, significantly affect the threshold voltage and mobility of devices. In this paper, we propose the first work to consider the three major sources of LDEs during analog placement. We first transform the three LDE models into nonlinear analytical placement models. Then an LDE-aware analytical analog placement algorithm is presented to mitigate the influence of the LDEs while improving circuit performance. Experimental results show that our placement algorithm can effectively and efficiently reduce the LDE-induced variations and improve circuit performance.

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“…To handle LDE by unintentional and intentional stresses, several LDE models exist based on a physical approach, but these have been focused on one-dimensional effects or limited layout parameters tested down to 45 nm technology node [5][6][7][8].…”

Section: Introductionmentioning

confidence: 99%

STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process

Jang

Bardon

Yakimets

et al. 2013

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

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As CMOS technology goes into the nanoscale regime, the impact of layout on the device performance becomes increasingly important. In this paper, we propose a physicsbased analytical model for Layout Dependent Effects (LDE) due to shallow trench isolation (STI) stress in 28 nm technology using "gate-last" process (Replacement Gate -RMG). The impact of active size and active width are considered and the model links between stress and device parameters such as the mobility and threshold voltage. The model is validated with experimental data. In addition, we investigate the impact of embedded Silicon-Germanium source/drain (eSiGe S/D) stressors in PMOS. Stronger mobility degradation is predicted for small width devices once eSiGe S/D is used. It results in a larger drop of normalized current (μA/μm) (-16%) once compared to transistors without eSiGe (-7%).

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A Framework for Layout-Dependent STI Stress Analysis and Stress-Aware Circuit Optimization

Cited by 19 publications

References 25 publications

The impact of shallow trench isolation effects on circuit performance

The impact of shallow trench isolation effects on circuit performance

Layout-dependent-effects-aware analytical analog placement

STI and eSiGe source/drain epitaxy induced stress modeling in 28 nm technology with replacement gate (RMG) process

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