The impact of shallow trench isolation effects on circuit performance

Abstract

Abstract-In nanometer technologies, shallow trench isolation (STI) induces thermal residual stress in active silicon due to post-manufacturing thermal mismatch. The amount of STI around an active region depends on the layout of the design, and the biaxial stress due to STI results in placement-dependent variations in the the transistor mobilities and threshold voltages of the active devices. An analytical model based on inclusion theory in micromechanics is employed to accurately estimate the stresses and the strains induced in the active region by the surrounding STI in the layout. The induced changes in mobility and threshold voltage changes are computed at the transistor level, and then propagated to the gate and circuit levels to predict circuit-level delay and leakage power for a given placement.

Characterization and Modeling of Mismatch in Cryo-CMOS

“…Apart from the mobility change, V TH is also found to shift for the outer most devices in Fig. 15c and f, which can also be attributed to mechanical stress, as also reported in [24] and [33].…”

“…Additionally, prior works also report deviations from the often encountered compressive, longitudinal (i.e., parallel to device current), uni-axial stress. In [24] it is shown that apart from the longitudinal stress component also the transverse component needs to be taken into account, which, if compressive, can degrade PMOS mobility. In [33] PMOS insensitivity to STI stress is reported, which was attributed to the wafer crystal orientation.…”

“…As matching deteriorates at cryogenic temperatures, it is worthwhile to investigate the effect of dummy devices on parameter variability at these low temperatures. This is especially interesting, as an increase in mechanical-stress-induced mismatch can be expected due to a significant thermal expansion/contraction at very low temperatures [24]. For this experiment I DSAT , V TH and β were extracted from devices placed in linear arrays.…”

Design procedure for multifinger MOSFET two‐stage OTA with shallow trench isolation effect

“…In [9], an analytical model based on inclusion theory in micromechanics is employed to accurately estimate the stresses and the strains induced in the active region by the surrounding STI in the layout. The induced changes in mobility and threshold voltage changes are computed at the transistor level, and then propagated to the gate and circuit levels to predict circuit‐level delay and leakage power for a given placement.…”

“…In addition, as the MOSFET sizes reach the nanoscale regime, a new type of variability was induced known as layout‐dependent effects (LDEs) [2–24], which becomes a critical issue in modern analogue and mixed‐signal circuit designs and is used to be the secondary concern of the circuit design. In particular, two dominant LDEs such as shallow trench isolation (STI) [8–19] and well proximity effect (WPE) [4, 20] are found to significantly affect the threshold voltage and mobility of devices in advanced technology nodes. This is true even in the general analogue integrated circuit building blocks.…”