A formal framework for high level synthesis

Abstract

In this paper, we propose a new approach to formal synthesis which focuses on the generation of verification-friendly circuits. Starting from a high-level implementation description, which may result from the application of usual scheduling and allocation algorithms, hardware is automatically synthesized. The target architecture is based on handshake processes, modules which communicate by a simple synchronizing handshake protocol. The circuits result from the application of only a few basic operations like synchronization, sequential execution or iteration of base handshake processes. Each process is guided by an abstract theorem that is used to derive proof obligations, to be justified after synthesis. Automation has been achieved to the extend that only those "relevant" proof obligations remain to be proven manually, e.g. theorems for data-dependent loops and lemmata about the used data types. The process-oriented implementation language is enriched by loop invariants. If those are given prior to the synthesis process and the underlying data types are only Booleans, i.e. finite-length bitvectors, then the complete synthesis and verification process runs automatically.

A refinement calculus for the synthesis of verified hardware descriptions in VHDL

“…The general technique is to express the desired circuit succinctly using higher-order circuit combinators and then prove that the functionality is as required (e.g., see Kropf et al [1994]). …”