Formal synthesis in circuit design — A classification and survey

Abstract

Abstract. This article gives a survey on different methods of formal synthesis. We define what we mean by the term formal synthesis and delimit it from the other formal methods that can also be used to guarantee the correctness of an implementation. A possible classification scheme for formal synthesis methods is then introduced, based on which some significant research activities are classified and summarized. We also briefly introduce our own approach towards the formal synthesis of hardware. Finally, we compare these approaches from different points of view.

Automatic correct scheduling of control flow intensive behavioral descriptions in formal synthesis

“…Yet, most formal synthesis approaches deal only with lower levels of abstraction (RT-and gate level) [11] or are restricted to acyclic data flow descriptions at the algorithmic level [8]. Also, they often cover only parts of the synthesis process, e. g. , the scheduling [12].…”

Automatic verification of scheduling results in high-level synthesis

“…Related work: According to [12], synthesis-verification maybe divided into pre-synthesis verification of synthesisalgorithms (e.g., [14]), formal synthesis where the constructive steps are embedded into a theorem prover (e.g., [3]), and post-synthesis verification where the synthesized results are verified afterwards (e.g., [13]). While most methods of post-synthesis verification use theorem proving techniques, a graph-based method was proposed in [8].…”

Formal Synthesis at the Algorithmic Level

“…Existing approaches in the area of formal synthesis deal with lower levels of abstraction (register-transfer (RT) level, gate level) [8,9,6,10,11] or with pure dataflow graphs at the algorithmic level [12]. This paper addresses formal synthesis at the algorithmic level.…”