2000 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.00CH37104)
DOI: 10.1109/vlsit.2000.852795
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A flash EEPROM cell with self-aligned trench transistor and isolation structure

Abstract: For furure highdensity contactless-NOR-type flash EEPROMs, a new memory cell with self-alipxl trench transistor & isolation structure has been propom$ and its feasibility was demonstratedThe short channel e f f i was suppressed markedly down to the f A m size (F) of 0.14 pn with the tunnel oxide thickness of 9 nm, and excellent endurance performance (>lo5 Fowler-Nordheim writelerase cycles) of the memory cell with the am of 0.16 pn2 (8F2, F4.14 pn) was realized.

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“…To solve this misalignment effect, a self-aligned contact (SAC) method is essential. 4) However, since the SAC method in a NOR flash cell suffers from a high bias above 4 V in a bit line for hot carrier injection programming, it is very severe project. To avoid gate to contact leakage in SAC, an enlarged metal contact (EMC) scheme is preferred.…”
Section: Control Of Misalignment For Gate To Contactmentioning
confidence: 99%
“…To solve this misalignment effect, a self-aligned contact (SAC) method is essential. 4) However, since the SAC method in a NOR flash cell suffers from a high bias above 4 V in a bit line for hot carrier injection programming, it is very severe project. To avoid gate to contact leakage in SAC, an enlarged metal contact (EMC) scheme is preferred.…”
Section: Control Of Misalignment For Gate To Contactmentioning
confidence: 99%