A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter

Tanihata, M.; Waho, Takao

doi:10.1109/ismvl.2006.5

Cited by 7 publications

(7 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To address this issue while hoping to retain its advantages, one idea is to maintain the width of the active feedback pulse as fixed as possible [15], hence to reduce the dominant pulse-width jitter. While this is well understood theoretically in literature, it is recent that circuits are proposed to generate a FWP (Fixed-Width Pulse) for active feedback [30,31]. One recently proposed method to use FWP RZ feedback is illustrated by the gate-level schematic in Figure 4 (simplified from the original circuit in [30,31]).…”

Section: Review Of Previous Workmentioning

confidence: 99%

“…While this is well understood theoretically in literature, it is recent that circuits are proposed to generate a FWP (Fixed-Width Pulse) for active feedback [30,31]. One recently proposed method to use FWP RZ feedback is illustrated by the gate-level schematic in Figure 4 (simplified from the original circuit in [30,31]). Assuming CLK J is the original jittered clock with ICJ at rising/falling edges, the resulting signal CLK J ND has a pulse of fixed-width td 2 set by the first inverter chain.…”

Section: Review Of Previous Workmentioning

confidence: 99%

“…Note that the fixed pulse width would provide a constant amount of feedback charge, hence eliminating pulse-width jitter otherwise caused by . The superior effectiveness of the FWP method has been shown in [15,30,31] with up to 33 dB of jitter noise reduction in example designs. However, there are some limitations of the FWP feedback.…”

Section: Review Of Previous Workmentioning

confidence: 99%

See 2 more Smart Citations

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Chang

Tang

2017

JLPEA

View full text Add to dashboard Cite

Abstract:It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While the effectiveness to reduce clock jitter effects may be of most importance in this comparison, we also consider other performance metrics such as circuit complexity and overhead to implement the technique, power consumption overhead of technique, synthesis complexity incurred in system-level design, extensibility of the technique from single-bit to multi-bit operation, and robustness to process variation. When clock jitter is relatively large, the fixed-width pulse feedback technique is most effective to reduce clock jitter effects among all techniques at high sampling frequency, while switched-capacitor-resistor and switched-shaped current techniques have best performance at medium frequency or below.

show abstract

Section: Review Of Previous Workmentioning

confidence: 99%

Section: Review Of Previous Workmentioning

confidence: 99%

Section: Review Of Previous Workmentioning

confidence: 99%

See 1 more Smart Citation

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Chang

Tang

2017

JLPEA

View full text Add to dashboard Cite

show abstract

“…However, the circuit for SSI may be difficult to implement as it requires extensive sizing and tuning to achieve precise transistor operation in different regions, As reducing pulse-width jitter is most important to improve the performance of CTDSM in the presence of clock jitter, one idea along this line is to maintain the feedback pulse width as fixed as possible [9]. While this is well understood, it is recent that circuits are proposed and used to generate a FWP (Fixed-Width Pulse) feedback [17][18][19]. A simple illustration of a FWP feedback by the gate-level schematic is given in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

Feasibility analysis of the fixed-width pulse RZ feedback to reduce clock jitter effects in lowpass continuous-time ΔΣ modulators

Chang

Tang

2013

2013 IEEE 56th International Midwest Symposium on Circuits and Systems (MWSCAS)

View full text Add to dashboard Cite

A recently proposed method to reduce clock jitter effects in continuous-time Delta-Sigma modulators is to generate a return-to-zero feedback with a fixed-width pulse for active feedback. In practice, the pulse width is subject to noise effects causing jitter of the pulse width itself. Therefore, jitter of the pulse width, though not the clock, may still degrade the performance of Delta-Sigma modulators. In this brief, we investigate practical feasibility of the method. It is shown that jitter of the pulse width could be conditionally much smaller than that of the clock, which therefore reduces clock jitter effects.

show abstract

“…By adding a constant delay to the feedback pulse and subtract the delayed pulse from the original one is also proposed [14], [15]. In this approach, the resulting pulse width is determined by the delay time, and independent of the clock jitter.…”

Section: Introductionmentioning

confidence: 99%

A bandpass continuous-time ΣΔ modulator using a parallel-DAC to reduce jitter sensitivity

Adachi

Machida

Waho

2009

2009 IEEE International Symposium on Circuits and Systems

View full text Add to dashboard Cite

A simple technique to reduce jitter sensitivity in the bandpass continuous-time delta-sigma modulator is presented. The feedback path in the modulator consists of parallel-connected unit-DACs that are driven by clocks with independent jitters. The outputs of the DACs are summed to form the feedback signal, so that the jitter effects are averaged out. Behavioral simulation shows that the signal-to-noise ratio (SNR) of the proposed modulator is improved by around 10dB by using 10 unit-DACs. It is also shown that the SNR is not sensitive to the mismatch in the unit-DAC output levels.

show abstract

A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter

Cited by 7 publications

References 5 publications

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Feasibility analysis of the fixed-width pulse RZ feedback to reduce clock jitter effects in lowpass continuous-time ΔΣ modulators

A bandpass continuous-time ΣΔ modulator using a parallel-DAC to reduce jitter sensitivity

Contact Info

Product

Resources

About

A Feedback-Signal Shaping Technique for Multi-Level Continuous-Time Delta-Sigma Modulators with Clock-Jitter

Cited by 7 publications

References 5 publications

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Feasibility analysis of the fixed-width pulse RZ feedback to reduce clock jitter effects in lowpass continuous-time &#x0394;&#x03A3; modulators

A bandpass continuous-time &#x03A3;&#x0394; modulator using a parallel-DAC to reduce jitter sensitivity

Contact Info

Product

Resources

About

Feasibility analysis of the fixed-width pulse RZ feedback to reduce clock jitter effects in lowpass continuous-time ΔΣ modulators

A bandpass continuous-time ΣΔ modulator using a parallel-DAC to reduce jitter sensitivity