A bandpass continuous-time ΣΔ modulator using a parallel-DAC to reduce jitter sensitivity

Abstract

A simple technique to reduce jitter sensitivity in the bandpass continuous-time delta-sigma modulator is presented. The feedback path in the modulator consists of parallel-connected unit-DACs that are driven by clocks with independent jitters. The outputs of the DACs are summed to form the feedback signal, so that the jitter effects are averaged out. Behavioral simulation shows that the signal-to-noise ratio (SNR) of the proposed modulator is improved by around 10dB by using 10 unit-DACs. It is also shown that the SNR is not sensitive to the mismatch in the unit-DAC output levels.