Feasibility analysis of the fixed-width pulse RZ feedback to reduce clock jitter effects in lowpass continuous-time ΔΣ modulators

Abstract

A recently proposed method to reduce clock jitter effects in continuous-time Delta-Sigma modulators is to generate a return-to-zero feedback with a fixed-width pulse for active feedback. In practice, the pulse width is subject to noise effects causing jitter of the pulse width itself. Therefore, jitter of the pulse width, though not the clock, may still degrade the performance of Delta-Sigma modulators. In this brief, we investigate practical feasibility of the method. It is shown that jitter of the pulse width could be conditionally much smaller than that of the clock, which therefore reduces clock jitter effects.

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

“…It is noted that process variation does not cause jitter induced charge error but only frequency response shift, which causes little performance degradation. As studied in [39], even with a large variation range (e.g., −20% to +30%) of the active feedback pulse of td 2 , there is no notable performance degradation (especially if compensation was used). However, under process variation, the current decreasing rate for SCR feedback or the operation region for SSI feedback changes, which may cause increasing jitter induced charge error and frequency response shift.…”