A fault simulation method for crosstalk faults in synchronous sequential circuits

Itazaki, Noriyoshi; Idomoto, Yasutaka; Kinoshita, K.

doi:10.1109/ftcs.1996.534592

Cited by 17 publications

(10 citation statements)

References 3 publications

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“…Crosstalk is caused by parasitic coupling between adjacent lines. Crosstalk effects can be divided into two types: crosstalk-induced pulse [1]- [4] and crosstalk-induced delay [2]- [4]. However, as far as crosstalk-induced delays are concerned (the focus of this paper), the existing literature has been limited only to the study of crosstalk-induced delay faults in combinational circuits.…”

Section: Introductionmentioning

confidence: 99%

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Takahashi

Keller

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-In this paper, we describe a method of identifying a set of target crosstalk faults which may need to be tested in synchronous sequential circuits. Our method classifies the pairs of aggressor and victim lines, using topological and timing information, to deduce a set of target crosstalk faults. In this process, our method also identifies the false crosstalk faults that need not (and/or cannot) be tested in synchronous sequential circuits. Experimental results for ISCAS'89 and ITC'99 benchmark circuits show that the proposed method is CPU time efficient in obtaining the reduced lists of the target crosstalk faults. Also, the lists of the target crosstalk faults obtained by our method are substantially smaller than the sets of all possible combinations of faults.Index Terms-Crosstalk faults, lists of the target crosstalk faults, synchronous sequential circuits.

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Section: Introductionmentioning

confidence: 99%

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Takahashi

Keller

et al. 2005

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…Moreover, since crosstalk faults in the logic circuit are a relatively new problem, there are few studies on test methods dealing with such faults [1][2][3][4][5][6]. Toward further miniaturization and high-speed implementation of future logic circuits, it is expected that crosstalk faults will increasingly become an important problem.…”

Section: Introductionmentioning

confidence: 99%

Built‐in Self‐Test for crosstalk faults in a digital VLSI

Shimizu

Itazaki

Kinoshita

2002

Systems & Computers in Japan

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SUMMARYAccompanying high-integration and high-speed implementation of VLSI in recent years, new faults which cannot be classified in the category of conventional fault models have become a problem. Among these new faults, we will deal with crosstalk faults in this paper. Because of excitation and propagation of the crosstalk faults in the detection of these faults, two successive test vectors are required and thus their generation is difficult. Moreover, it is necessary in the sequential circuit to consider the problem of timing such as gate delay time and FF setup time in the circuit. For that reason, it has been difficult to realize a high fault coverage in the test vector generation methods proposed so far. To solve these problems, we will newly propose in this paper a Built-In Self-Test (BIST) method which can detect the crosstalk faults. This method can be realized by a relatively small area overhead; moreover, by adopting a circuit configuration during simulation which is different from the one during test, the simulation time is shortened. In this way, testing of large-scale circuits has been made possible. We have performed an evaluation on the fault coverage for several benchmark circuits and shown that this method is effective for crosstalk faults.

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“…We ran our simulator on several ISCAS'89 [2] benchmark circuits, using vectors provided by FASTEST [6] as test sequences. For comparison purpose, we ran the same benchmark circuits and test sequences on the conventional crosstalk fault simulator originally used in [4] and updated in [7]. Table 1 summarizes the information about benchmark circuits and test sequences used in the experiments.…”

Section: Resultsmentioning

confidence: 99%

“…A simulator for crosstalk-pulse faults in sequential circuits was developed and presented in [4]. A simple update of this simulator with modifications suitable for crosstalk fault diagnosis tool is described in [7].…”

Section: Previous Work and Contributionsmentioning

confidence: 99%

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A concurrent fault simulation for crosstalk faults in sequential circuits

Phadoongsidhi

Le²,

Saluja

Proceedings of the 11th Asian Test Symposium, 2002. (ATS '02).

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Existing principle for crosstalk fault simulation requires the storage of waveform representation at each node in the circuit throughout a time frame. At the end of each time frame a pair of waveforms, one belonging to an aggressor node, and one depicting a victim node, is inspected. If the fault is captured, it will be simulated until it is either detected or the test vectors are exhausted. This fault detection method can require a prohibitive amount of computation time for a large sequential circuit with high number of possible fault pairs to be tested. With our simulation technique introduced in this paper, these operations can be processed concurrently for many faults. The fault list dynamically adjusts itself during the simulation to accommodate fault injection and fault dropping. Experimental results on ISCAS'89 benchmark circuits show that a substantial improvement in CPU time over a conventional method is achieved with a trade-off in the amount of memory consumed.

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A fault simulation method for crosstalk faults in synchronous sequential circuits

Cited by 17 publications

References 3 publications

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Built‐in Self‐Test for crosstalk faults in a digital VLSI

A concurrent fault simulation for crosstalk faults in sequential circuits

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