A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Takahashi, Hiroshi; Keller, Kai; Le, Kim; Saluja, Kewal K.; Takamatsu, Yasushi

doi:10.1109/tcad.2004.837733

Cited by 16 publications

(11 citation statements)

References 16 publications

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“…If it overlaps, the pair form a target cross-talk fault (Takahashi et al 2005). The selection of critical paths, number of victims in the critical path, and the total number of target cross-talk delay faults are found using static timing analysis.…”

Section: Static Timing Analysismentioning

confidence: 99%

Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems

Bhuvaneswari¹

2015

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Section: Static Timing Analysismentioning

confidence: 99%

Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems

Bhuvaneswari¹

2015

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“…The method uses logical level implementation of the circuit and does not require layout information [16]. It is more amenable to the time to market need of designs.…”

Section: Crosstalk Fault List Generatormentioning

confidence: 99%

Test Generation for Crosstalk‐Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Jayanthy¹,

Bhuvaneswari

Sujitha

2012

VLSI Design

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As design trends move toward nanometer technology, new problems due to noise effects lead to a decrease in reliability and performance of VLSI circuits. Crosstalk is one such noise effect which affects the timing behaviour of circuits. In this paper, an efficient Automatic Test Pattern Generation (ATPG) method based on a modified Fanout Oriented (FAN) to detect crosstalk-induced delay faults in VLSI circuits is presented. Tests are generated for ISCAS_85 and enhanced scan version of ISCAS_89 benchmark circuits. Experimental results demonstrate that the test program gives better fault coverage, less number of backtracks, and hence reduced test generation time for most of the benchmark circuits when compared to modified Path-Oriented Decision Making (PODEM) based ATPG. The number of transitions is also reduced thus reducing the power dissipation of the circuit.

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“…If for some reasons the delays (transistor or interconnect) change, such as due to fabrication defects or cross-talk effects [7,11], an incorrect datum may be loaded into the flip-flop or observed at the primary output. Such a failure is called a path-delay fault (PDF).…”

Section: Requirements For Pdf Testsmentioning

confidence: 99%

“…The reduction in feature size coupled with the increase in operating speed introduces new failure models, including the presence of path-delay faults (PDF) [3] due to manufacturing defects [6,7] or crosstalk [11]. Considerable literature exists that deals with enhanced serial-scan architecture, with hold latches, for application of two pattern tests [3,4].…”

Section: Introductionmentioning

confidence: 99%

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan

Baik

Saluja

2007

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

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Studies of Random-Access Scan (RAS) architecture have largely limited their scope to reduce test application time, test volume and test power to detect conventional stuck-at faults. In this paper we propose an enhanced RAS latch design for two pattern tests. The proposed latch is a minor modification of the RAS latch and is well suited for delayfault tests. In contrast, the traditional serial scan latch needs a major enhancement. As a result the RAS may offer a hardware advantage while the test time is nearly halved over the serial scan design. We demonstrate the test time advantage in this paper for various test sets for benchmark circuits and we argue that the advantage is even larger when test sets are generated for RAS architecture in mind, as well as by the exploitation of unspecified bits in test vectors.20th International Conference on VLSI Design (VLSID'07) 0-7695-2762-0/07 $20.00

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A method for reducing the target fault list of crosstalk faults in synchronous sequential circuits

Cited by 16 publications

References 16 publications

Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems

Application of Evolutionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems

Test Generation for Crosstalk‐Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm

Test Time Reduction to Test for Path-Delay Faults using Enhanced Random-Access Scan

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