A fast parallel multiplier-accumulator using the modified Booth algorithm

El-Guibaly, F.

doi:10.1109/82.868458

Cited by 84 publications

(31 citation statements)

References 20 publications

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“…Another efficient algorithm known as the modified Booth or radix-4 Booth algorithm was proposed by McSorley [14]. The MBE algorithm is an efficient way in parallel multiplier design since it can reduce the number of partial product rows to be added by half, thus reducing the size and enhancing the speed of the PPRT [15][16][17]. In this section, Booth encoding algorithm and RB signed-digit number representations will be discussed.…”

Section: Radix-4 Booth Encoding and Redundant Binary Signed-digitmentioning

confidence: 99%

A New Redundant Binary Partial Product Generator for Fast 2n-Bit Multiplier Design

Chen

et al. 2014

2014 IEEE 17th International Conference on Computational Science and Engineering

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The radix-4 Booth encoding or Modified Booth encoding (MBE) has been widely adopted in partial products generator to design high-speed redundant binary (RB) multipliers. Due to the existence of an error-correcting word (ECW) generated by MBE and RB encoding, the RB multiplier generates an additional RB partial product rows. An extra RB partial product accumulator (RBPPA) stage is needed for 2 n -b RB MBE multiplier. The higher radix Booth algorithm than radix-4 can be adopted to reduce the number of partial products. However, the Booth encoding is not efficient because of the difficulty in generating hard multiples. The hard multiples problem in RB multiplier can be resolved by difference of two simple power-of-two multiples. This paper presents a new radix-16 RB Booth Encoding (RBBE-4) to avoid the hard multiple of high-radix Booth encoding without incurring any ECW. The proposed method leads to make highspeed and low-power RB multipliers. The experimental results show that the proposed RBBE-4 multiplier achieves significant improvement in delay and power consumption compared with the RB MBE multiplier and the current reported best RBBE-4 multipliers.

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Section: Radix-4 Booth Encoding and Redundant Binary Signed-digitmentioning

confidence: 99%

A New Redundant Binary Partial Product Generator for Fast 2n-Bit Multiplier Design

Chen

et al. 2014

2014 IEEE 17th International Conference on Computational Science and Engineering

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“…In order to increase the performance of the MAC operation, Elguibaly [10] proposed the fusion of the accumulation circuit with the unit which adds the partial products generated during the multiplication. The addition is performed using a hybrid carry-save (CS) array.…”

Section: Introductionmentioning

confidence: 99%

High performance MAC designs

Eftaxiopoulos

Zervakis

Pekmestzi

et al. 2014

2014 9th International Design and Test Symposium (IDT)

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In this paper we propose two high performance multiplication-accumulation (MAC) designs. Targeting to operate at higher frequency, we investigate two different techniques based on the carry-save representation in order to reduce the delay impact of the accumulation process on the MAC operation. We conducted detailed experimental measurements to verify the advantages of the proposed MAC designs compared to two existing ones. Both the proposed designs operate at higher frequency without any losses in the area occupied or the power consumed.

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“…In the final step, two last rows are added together to compute the final multiplier result. Many different kinds of high-speed adder have been presented such as Carry-save Adder [4], Carry Look Ahead Adder (CLA) [10], [11], etc. However, it can be proven that there is a part of the final multiplier result can be computed at the end of each rowaddition processing in step 2.…”

Section: Introductionmentioning

confidence: 99%

A high-speed unsigned 32-bit multiplier based on booth-encoder and wallace-tree modifications

Luu

Hoang

Bui

et al. 2014

2014 International Conference on Advanced Technologies for Communications (ATC 2014)

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The delay of the multiplier plays a critical role in many high-speed implementations and processors such as RISC, DSP, and image processing cores, etc. In this paper, a design of unsigned 32-bit multiplier is proposed, aiming to achieve the best timing performance with an appropriate area. The proposed architecture consists of a modified Radix-4 Booth encoder, a modified Wallace Tree adder, and a Carry Look Ahead adder. The design has been verified successfully on DE2-115 and then synthesized to ASIC implementation. The FPGAbased experimental result shows that it has the resources of 1788 ALUTs. The synthesized result occupies an area of 58.28 mm 2 with 4.13 ns total delay (i.e. 242.13MHz maximum frequency).

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A fast parallel multiplier-accumulator using the modified Booth algorithm

Cited by 84 publications

References 20 publications

A New Redundant Binary Partial Product Generator for Fast 2n-Bit Multiplier Design

A New Redundant Binary Partial Product Generator for Fast 2n-Bit Multiplier Design

High performance MAC designs

A high-speed unsigned 32-bit multiplier based on booth-encoder and wallace-tree modifications

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