High performance MAC designs

Eftaxiopoulos, Nikolaos; Zervakis, Georgios; Pekmestzi, Kiamal; Efstathiou, C.

doi:10.1109/idt.2014.7038582

Cited by 2 publications

(4 citation statements)

References 14 publications

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“…Critical path of [18] and Conv_Wa include the

\log_{2} n

CSA stages, whereas the proposed design includes (

2.29 + 1.71 \log_{2} false(false(n / 2 false) + 1 false)

) stages. Therefore, the critical path delay of proposed design is greater than [18] and Conv_Wa [17] and Figure 5 in [20] contains

false(3 + \log_{2} n false)

and (

1 + \log_{2} n

) CSA levels in critical path, which are less than proposed design. So, critical path delay for [17] and Figure 5 in [20] are less than proposed design.…”

Section: Design Modelling Implementation and Resultsmentioning

confidence: 97%

“…Therefore, the critical path delay of proposed design is greater than [18] and Conv_Wa [17] and Figure 5 in [20] contains

false(3 + \log_{2} n false)

and (

1 + \log_{2} n

) CSA levels in critical path, which are less than proposed design. So, critical path delay for [17] and Figure 5 in [20] are less than proposed design. The critical path of [8] includes only one

\log_{2} 2 n

bit CLA.…”

Section: Design Modelling Implementation and Resultsmentioning

confidence: 97%

“…1c are not used during 16 × 16 bit MAC mode. In most of the non-vector MAC designs [6][7][8][18][19][20][21], the flexibility to perform multiple MAC operations is absent. For example, second, third, and fourth quarters of Figs.…”

Section: Related Workmentioning

confidence: 99%

“…The merged Wallace tree‐based MAC is proposed in [19], where the previous MAC result is added along with present multiplication. In [20], the previous MAC result is added along with the sum and carry from the last carry save stage of the Wallace tree multiplier. In [21], memory‐based conventional MAC is designed, where one of the operand will be sent to the multiplier from the memory.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Quadruple throughput fixed point quarter precision multiply accumulate circuit design

Basiri

Mohammad

2017

IET Computers & Digital Techniques

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This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier-based double throughput MAC.

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“…Critical path of [18] and Conv_Wa include the

\log_{2} n

CSA stages, whereas the proposed design includes (

2.29 + 1.71 \log_{2} false(false(n / 2 false) + 1 false)

) stages. Therefore, the critical path delay of proposed design is greater than [18] and Conv_Wa [17] and Figure 5 in [20] contains

false(3 + \log_{2} n false)

and (

1 + \log_{2} n

) CSA levels in critical path, which are less than proposed design. So, critical path delay for [17] and Figure 5 in [20] are less than proposed design.…”

Section: Design Modelling Implementation and Resultsmentioning

confidence: 97%

“…Therefore, the critical path delay of proposed design is greater than [18] and Conv_Wa [17] and Figure 5 in [20] contains

false(3 + \log_{2} n false)

and (

1 + \log_{2} n

) CSA levels in critical path, which are less than proposed design. So, critical path delay for [17] and Figure 5 in [20] are less than proposed design. The critical path of [8] includes only one