A fast macro based compilation methodology for partially reconfigurable FPGA designs

Handa, Manish; Radhakrishnan, R.; Mukherjee, M.; Vemuri, Ranga

doi:10.1109/icvd.2003.1183120

Cited by 3 publications

(1 citation statement)

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“…In such a scenario it is possible to partition the desired application into a subset of n smaller tasks, each one fitting on the chip. The FPGA will be reconfigured at runtime to execute the various tasks: this idea has been named time partitioning, and has been extensively studied in literature [8][9][10]. A further improvement in FPGA technology allows modern boards to reconfigure only some of the logic gates.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Reconfigurability in Embedded System Design

Rana

Santambrogio

Sciuto

2007

2007 IEEE International Symposium on Circuits and Systems (ISCAS)

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Nowadays, dynamic reconfigurable embedded systems are widely used, since they have the capability to modify their functionalities, adding or removing components and modify interconnections among them. The basic idea behind these systems is to have the system autonomously modify its functionalities according to the application's changes. This paper describes the area of reconfigurable embedded systems presenting both architectural and methodological aspects trying to point out common features and needs. After a brief introduction, an overview of the models, of the reconfigurable architectures, and of the design methodologies will be presented.

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Section: Introductionmentioning

confidence: 99%