A fast full-wave algorithm to generate low order electromagnetic scattering models

Klemas, Thomas J.; Daniel, Luca; White, Jacob K.

doi:10.1109/aps.2005.1551755

Cited by 4 publications

(1 citation statement)

References 4 publications

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“…Our new method to rescale the ETAS blocks dramatically improved conditioning and facilitated MOR. SPPF-FMOR has been extended for PFFT sparsification [8] and to create ROMs based on multiple expansion points (multi-point MOR). Future work will involve generating passive time domain models, examining elaborate structures, analyzing cost, and constructing multi-parameter ROMs.…”

Section: Discussionmentioning

confidence: 99%

Segregation by primary phase factors: a full-wave algorithm for model order reduction

Klemas

Daniel

White

2005

Proceedings. 42nd Design Automation Conference, 2005.

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Existing Full-wave Model Order Reduction (FMOR) approaches are based on Expanded Taylor Series Approximations (ETAS) of the oscillatory full-wave system matrix. The accuracy of such approaches hinges on the worst case interaction distances, producing accurate models over a very narrow band of frequencies. In this paper we present Segregation by Primary Phase Factors (SPPF), a novel algorithm for FMOR enabling wideband interconnect impedance analysis. SPPF extracts exponential terms (primary phase factors) and then approximates the smoother remainder with an ETAS, thus resulting in good accuracies over a very wide band of frequencies. We also present a technique to improve conditioning for the required computation. Example results are given for simple interconnect structures modeled using a discretized mixed potential integral equation formulation.

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Section: Discussionmentioning

confidence: 99%

Segregation by primary phase factors: a full-wave algorithm for model order reduction

Klemas

Daniel

White

2005

Proceedings. 42nd Design Automation Conference, 2005.

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Differentiate and deliver

Vleeschhouwer

Goldman

Park

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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For the past 25 years, the EDA industry has played a major role in the growth of the semiconductor industry, providing tools and services that have helped companies develop electronics products that permeate and improve every aspect of our daily lives.As the semiconductor industry moves into the nanometer era, they face many key questions when envisioning a new product. When do they want the product to reach the market? How will that product be differentiated? Where do they develop and manufacture that product?Less than a decade ago, these questions would have been answered completely independent of whatever EDA vendor a semiconductor company selected. However, in the nanometer era, the answers to these questions can be significantly influenced not only by EDA companies but also by the IP and pure-play foundries that make up the infrastructure of the semiconductor industry. In order to compete in a global marketplace, these companies must align their individual core competencies with those of the semiconductor industry to help IC companies create products with the optimal combination of performance, price, and time-to-market.In this panel, the CEOs of the three major EDA vendors, along with peers from the IP and manufacturing areas discuss these fundamental changes to the semiconductor industry, and the challenges of working together to help customers successfully bring new products to market. Jay Vleeschhouwer, a senior analyst for Merrill Lynch, will moderate a series of questions for the panelists from the customer's point of view that address how EDA, IP and pureplay foundries can impact the competitiveness of semiconductor companies and the products they develop.

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Logic soft errors in sub-65nm technologies design and CAD challenges

Mitra

Karnik

Seifert

et al. 2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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Logic soft errors are radiation induced transient errors in sequential elements (flip-flops and latches) and combinational logic. Robust enterprise platforms in sub-65nm technologies require designs with built-in logic soft error protection. Effective logic soft error protection requires solutions to the following three problems: (1) Accurate soft error rate estimation for combinational logic networks;(2) Automated estimation of system effects of logic soft errors, and identification of regions in a design that must be protected; and, (3) New cost-effective techniques for logic soft error protection, because classical fault-tolerance techniques are very expensive.

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A fast full-wave algorithm to generate low order electromagnetic scattering models

Cited by 4 publications

References 4 publications

Segregation by primary phase factors: a full-wave algorithm for model order reduction

Segregation by primary phase factors: a full-wave algorithm for model order reduction

Differentiate and deliver

Logic soft errors in sub-65nm technologies design and CAD challenges

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