Logic soft errors in sub-65nm technologies design and CAD challenges

Mitra, Subhasish; Karnik, Tanay; Seifert, N.; Zhang, Ming

doi:10.1145/1065579.1065585

Cited by 54 publications

(10 citation statements)

References 263 publications

(22 reference statements)

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“…The amplitude of the hazard pulse will be reduced, and eventually the hazard pulse may disappear. However, since most logic gates are nonlinear circuits with a substantial voltage gain, low-frequency pulses with sufficient initial amplitude will be amplified [22].…”

Section: Soft Errorsmentioning

confidence: 99%

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Oughali

2014

Microelectronics Reliability

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Section: Soft Errorsmentioning

confidence: 99%

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

Oughali

2014

Microelectronics Reliability

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“…3) Electrical masking occurs when the pulse resulting from SEU attenuates as it travels through logic gates and wires. In addition, pulses outside the cutoff frequency of CMOS elements will be faded out [11], [26]. Therefore, we assign a probability ρ to each logic gate to indicate how likely a pulse resulting from SEU can survive to the end and cause an error in the output.…”

Section: B Seumentioning

confidence: 99%

General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing

Dabiri

Nahapetian

Massey

et al. 2008

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Power consumption has emerged as the premier and most constraining aspect in modern microprocessor and application-specific designs. Gate sizing has been shown to be one of the most effective methods for power (and area) reduction in CMOS digital circuits. Recently, as the feature size of logic gates (and transistors) is becoming smaller and smaller, the effect of soft-error rates caused by single-event upsets (SEUs) is becoming exponentially greater. As a consequence of technology feature size reduction, the SEU rate for typical microprocessor logic at sea level will go from one in hundred years to one every minute. Unfortunately, the gate sizing requirements of power reduction and resiliency against SEU can be contradictory. 1) We consider the effects of gate sizing on SEU and incorporate the relationship between power reduction and SEU resiliency to develop a new method for power optimization under SEU constraints. 2) Although a nonlinear programming approach is a more obvious solution, we propose a convex programming formulation that can be solved efficiently. 3) Many of the optimal existing techniques for gate sizing deal with an exponential number of paths in the circuit. We prove that it is sufficient to consider a linear number of constraints. 4) We generalize our methodology to include nonlinear delay models and leakage power as well. As an important preprocessing step, we apply statistical modeling and validation techniques to quantify the impact of fault masking on the SEU rate. Furthermore, we adapt our method to incorporate process variation and evaluate our gate sizing technique under uncertainty. We evaluate the effectiveness of our methodology on ISCAS benchmarks and show that error rates can be reduced by a factor of 100%-200% while, on average, the power reduction is simultaneously decreased by less than 6%-10%, respectively, compared to the optimal power saving with no error rate constraints.

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“…The proposed experiments offer a high repair rate, close to the existing optimal algorithms. In [7], the problem of sub-65nm designs is described. Since it is stated that classical faulttolerance techniques for soft error detection are expensive, a recently developed Built-In-Soft-error-Resilience (BISER) technique is proposed, which seems effective for soft error blocking or detection.…”

Section: Introductionmentioning

confidence: 99%

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques

Ruano

Reyes

Maestro

et al. 2007

2007 IEEE Design and Diagnostics of Electronic Circuits and Systems

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Abstract-Logic Soft Errors caused by radiation are a major concern when working with circuits that need to operate in harsh environments, such as space or avionics applications, where soft errors are traditionally referred as Single Event Effects. In this paper, system knowledge-based hardening techniques using recursive structures for the implementation of moving average filters that provide protection against Single Event Upsets are evaluated through two fault injection systems based on simulation and emulation respectively. Fault injection campaigns show that system knowledge-based redundancy techniques can achieve the same level of dependability as standard redundancy techniques, such as Triple Modular Redundancy, while having optimal cost.

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Logic soft errors in sub-65nm technologies design and CAD challenges

Cited by 54 publications

References 263 publications

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits

General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing

An Experimental Analysis of SEU Sensitiveness on System Knowledge-based Hardening Techniques

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