The 20th Asia and South Pacific Design Automation Conference 2015
DOI: 10.1109/aspdac.2015.7059108
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A fast and accurate network-on-chip timing simulator with a flit propagation model

Ta-Cheng Hsu
1
,
Jun-Lin Chiu
2
,
Chao-Kai Yu
3
et al.
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Cited by 2 publications
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References 13 publications
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Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures

Eggenberger
1
,
Strobel
2
,
Radetzki
3
2016
2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)
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1
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Globally Asynchronous Locally Synchronous Simulation of NoCs on Many-Core Architectures

Eggenberger
1
,
Strobel
2
,
Radetzki
3
2016
2016 24th Euromicro International Conference on Parallel, Distributed, and Network-Based Processing (PDP)
2
0
1
0
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Optimization for application-specific packet-based on-chip interconnects using a cycle-accurate model

Shih
1
,
Huang
2
,
Liou
3
et al. 2017
2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT)
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