A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications

Suleiman, Adnan; Saleh, Hani; Hussein, A.; Akopian, David

doi:10.1109/iccd.2008.4751880

Cited by 13 publications

(4 citation statements)

References 19 publications

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“…Four single-port RAM memories are used in [32] combined with one radix-2 processing element. A scalable pipelined architecture is presented in [26] where two or four processing elements can be used with perfect shuffle permutation and data reordering. High energy-efficiency is achieved by using modern technology and low supply voltage.…”

Section: Methodsmentioning

confidence: 99%

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Low-Power Application-Specific Processor for FFT Computations

Pitkänen

Takala

2010

J Sign Process Syst

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Section: Methodsmentioning

confidence: 99%

“…FFT implementations can be divided to two categories: memory based, e.g., [25,31] or pipelines, e.g., [11,26,30]. Pipelined FFTs are usually used in short FFTs since as the size of the FFT increases, more intermediate storage is needed and memory is more efficient storage for large amount of data than registers and delay elements used in pipelines.…”

mentioning

confidence: 99%

Low-Power Application-Specific Processor for FFT Computations

Pitkänen

Takala

2010

J Sign Process Syst

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“…This can be applied sequentially as follows: Reordering operators can operate on two data indices at a time instead of three as shown in (7) [16] for further decomposition detail.…”

Section: Decompositions Of Perfect Shuffle (Unshuffle) Reorderingmentioning

confidence: 99%

Scalable interconnect networks for Discrete Cosine Transforms (DCT) for mobile and multimedia application

Hussein

Suleiman

Kerkiz

et al. 2010

2010 53rd IEEE International Midwest Symposium on Circuits and Systems

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Scalable architectures were proposed for Discrete Cosine Transform (DCT). Number of processing elements (PE) can be reduced significantly using partial column structure for computing the DCT transform. This feature is very desirable for multimedia applications usage in handheld devices. As per transform computation, data reordering is required between stages (columns) where intermediate computed values are saved in memory-like temporary locations called FIFO's. A scalable interconnect network for both global and local data reordering and its implementation is presented in this paper. Scalability is based on transform size and desired number of processing elements (PE). The structure gives choice flexibility of throughput vs. complexity (cost and area.) of the overall system.

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“…In some cases the length of the processed sequence is fixed but there exist also very flexible, variable length, and memory-based FFT implementations [GRH11]. A more detailed characterization of FFT architectures can be found in [SSHA08]. The implementation of the NTT on graphic cards is described in [Eme09].…”

Section: Previous Work Unrelated To Lattice-based Cryptographymentioning

confidence: 99%

Efficient implementation of ideal lattice-based cryptography

Pöppelmann¹

2017

It - Information Technology

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Digital signatures and public-key encryption are used to protect almost any secure communication channel on the Internet or between embedded devices. Currently, protocol designers and engineers usually rely on schemes that are either based on the factoring assumption (RSA) or on the hardness of the discrete logarithm problem (DSA/ECDSA). But in case of advances in classical cryptanalysis or progress on the development of quantum computers the hardness of these closely related problems might be seriously weakened. In order to prepare for such an event, research on alternatives is required to provide long-term security.In this thesis, we focus on the efficient implementation of such alternative public-key cryptosystems whose security is based on the intractability of certain computational problems on ideal lattices. While an extensive theoretical background exists for lattice-based and ideal latticebased cryptography, not much is known about the efficiency of practical instantiations, especially on constrained and cost-sensitive platforms. We thus investigate novel algorithms and implementation techniques for fast and flexible polynomial multiplication and Gaussian sampling and then use these building blocks to implement public-key encryption and signature schemes. The results provided in this thesis show that lattice-based schemes can be optimized for high performance or resource efficiency on embedded microcontrollers and reconfigurable hardware. Our implementations of a public-key encryption scheme based on the ring learning with errors problems (RLWE) or of the bimodal lattice signature scheme (BLISS) can even outperform classical ECC-and RSA-based implementations.Lattice-based cryptography can also be used to realize homomorphic cryptography that allows computation on encrypted data. However, due to the large parameter sets and complex operations required, even for simple homomorphic evaluation operations, the performance of these schemes is a major issue preventing practical usage. In this thesis we investigate options for acceleration of homomorphic cryptography in a cloud environment using reconfigurable hardware. We implement all evaluation operations of the YASHE homomorphic encryption scheme and propose methods to deal with large ciphertext and key sizes as well as limited memory bandwidth. KeywordsPost-quantum cryptography, public-key cryptosystem, embedded system, microcontroller, FPGA KurzfassungDigitale Signaturen und Public-Key-Verschlüsselung werden für den Schutz nahezu jeder sicheren Kommunikation über das Internet oder zwischen eingebetteten Systemen genutzt. Die Sicherheit basiert dabei entweder auf der Faktorisierungsannahme (RSA) oder der Annahme, dass es schwer ist, das diskrete Logarithmus-Problem (DSA/ECDSA) zu lösen. Durch Fortschritte in der klassischen Kryptoanalyse oder bei der Entwicklung von Quantencomputern könnten diese Probleme allerdings in Zukunft ernsthaft geschwächt oder gelöst werden. Daher ist Forschung zu alternativen Public-Key-Kryptosystemen erforderlich, die in ...

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A family of scalable FFT architectures and an implementation of 1024-point radix-2 FFT for real-time communications

Cited by 13 publications

References 19 publications

Low-Power Application-Specific Processor for FFT Computations

Low-Power Application-Specific Processor for FFT Computations

Scalable interconnect networks for Discrete Cosine Transforms (DCT) for mobile and multimedia application

Efficient implementation of ideal lattice-based cryptography

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