A Family of Low-Voltage Bulk-Driven CMOS Continuous-Time CMFB Circuits

Carrillo, Juan M.; Torelli, G.; Dominguez, M.A.; Pérez-Aloe, R.; Valverde, J.M.; Duque-Carrillo, J.F.

doi:10.1109/tcsii.2010.2068090

Cited by 29 publications

(9 citation statements)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In such a way, the negative feedback loop involving OTA I and VOA enforces the output CM level to be equal to V CM . Because the CM loop gain and bandwidth are both approximately the same as for a differential mode loop (for N = 8), then, the circuit provides fast and accurate operation [26] and can be frequency compensated with the same capacitances C C as the overall PGA.…”

Section: Voa With Cmfb Circuitmentioning

confidence: 99%

“…where C L is the assumed load capacitance. The formula (26) was derived assuming a 60°phase margin for the feedback loop (OTA II /VOA) [24]. It is worth to note, that because both OTAs in the PGA circuit operate as linear elements, no slewing effect is observed as long as the signal rate is not constrained by the main stage of VOA.…”

Section: Pga Designmentioning

confidence: 99%

“…This requires: I D11,12 ≥ g mI V DD (C L + C C )/C L . Therefore, if required, the currents given by (26) could be modified in order to meet the aforementioned condition and avoid slew rate limitation introduced by the main stage of VOA.…”

Section: Pga Designmentioning

confidence: 99%

See 2 more Smart Citations

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

Kulej

Khateb

2016

Circuit Theory & Apps

View full text Add to dashboard Cite

A new solution for an ultra low voltage bulk-driven programmable gain amplifier (PGA) is described in the paper. While implemented in a standard n-well 0.18-μm complementary metal-oxide-semiconductor (CMOS) process, the circuit operates from 0.3 V supply, and its voltage gain can be regulated from 0 to 18 dB with 6-dB steps. At minimum gain, the PGA offers nearly rail-to-rail input/output swing and the input referred thermal noise of 2.37 μV/Hz 1/2 , which results in a 63-dB dynamic range (DR). Besides, the total power consumption is 96 nW, the signal bandwidth is 2.95 kHz at 5-pF load capacitance and the thirdorder input intercept point (IIP 3 ) is 1.62 V. The circuit performance was simulated with LTspice. Copyright

show abstract

Section: Voa With Cmfb Circuitmentioning

confidence: 99%

Section: Pga Designmentioning

confidence: 99%

See 1 more Smart Citation

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

Kulej

Khateb

2016

Circuit Theory & Apps

View full text Add to dashboard Cite

show abstract

“…Figure 1 illustrates conceptual architecture of the CMFB. 3 The basic idea in this gure is to sense the level of the output CM voltage, compare it with a reference voltage and feedback the CM correction signal to the ampli¯er. The correction signal is a function of di®erence between output CM signal and the reference voltage.…”

Section: Introductionmentioning

confidence: 99%

A Fast and Low Settling Error Continuous-Time Common-Mode Feedback Circuit Based on Differential Difference Amplifier

Khaneshan

Naghavi

Nematzade

et al. 2014

J CIRCUIT SYST COMP

View full text Add to dashboard Cite

A high-speed and high-accuracy continuous-time common-mode feedback block (CMFB) is presented. To satisfy speed and accuracy requirements, some modi¯cations have been applied on di®erential di®erence ampli¯er (DDA) CMFB circuit. The proposed method is applied to a folded cascode op-amp with power supply of 3.3 V. In order to verify the proposed circuit, simulations are done in 0.35 m standard CMOS technology. In the worst condition when the output common-mode (CM) voltage is initialized to VCC or GND, only 1.1 ns is required to set the output CM voltage on the desired level. Also in a wide range of input CM voltage variations, the deviation of the output CM voltage from reference voltage is less than 6 mV, so simulation results con¯rm the expected accuracy and speed while simultaneously the proposed CMFB circuit preserves other characteristics of DDA CMFB circuit such as unity gain frequency, 3-dB bandwidth, phase margin and linearity. 1450065-3 J CIRCUIT SYST COMP 2014.23. Downloaded from www.worldscientific.com by FLINDERS UNIVERSITY LIBRARY on 02/03/15. For personal use only. A Fast and Low Settling Error Continuous-Time CM Feedback Circuit 1450065-13 J CIRCUIT SYST COMP 2014.23. Downloaded from www.worldscientific.com by FLINDERS UNIVERSITY LIBRARY on 02/03/15. For personal use only. A Fast and Low Settling Error Continuous-Time CM Feedback Circuit 1450065-15 J CIRCUIT SYST COMP 2014.23. Downloaded from www.worldscientific.com by FLINDERS UNIVERSITY LIBRARY on 02/03/15. For personal use only.

show abstract

“…Therefore, some considerations related to standard CMOS design and the clock phases minimization, makes AF-SHA among the most efficient architectures also compared to FOM of the SHA-less analog-to-digital converters (ADCs) [21,22]. Expanding upon the method reported in [23,24], this paper introduces a novel CMFB compensation technique, especially suited for DDA-based AF-SHA, but also applicable to a variety of time-discrete applications. Before proceeding any further, it is worth noting that by improving the CMFB gain, also the common-mode rejection ratio (CMRR) is enhanced [25,26].…”

Section: Introductionmentioning

confidence: 99%

An improved common-mode feedback loop for the differential-difference amplifier

Centurelli

Simonetti

Trifiletti

2012

Analog Integr Circ Sig Process

View full text Add to dashboard Cite

Unconditional stability of the high-gain amplifiers is a mandatory requirement for a reliable steady-state condition of time-discrete systems, especially for all blocks designed to sample-and-hold (S/H) circuits. Compared to differential path, the common-mode feedback loop is often affected by poles and zeros shifting that degrades the large signal response of the amplifiers. This drawback is made worse in some well-known topologies as the difference-differential amplifier (DDA) that shows non-constant transconductance and poor linearity. This work proposes a body-driven positive-feedback frequency compensation technique (BD-PFFC) to improve the linearity for precision DDA-based S/H applications. Theoretical calculations and circuit simulations carried out in a 0.13 mu m process are also given to demonstrate its validity

show abstract

A Family of Low-Voltage Bulk-Driven CMOS Continuous-Time CMFB Circuits

Cited by 29 publications

References 17 publications

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

0.3‐V bulk‐driven programmable gain amplifier in 0.18‐µm CMOS

A Fast and Low Settling Error Continuous-Time Common-Mode Feedback Circuit Based on Differential Difference Amplifier

An improved common-mode feedback loop for the differential-difference amplifier

Contact Info

Product

Resources

About