A dynamically reconfigurable asynchronous processor for low power applications

Fawaz, Khodor; Arslan, Tughrul; Khawam, S.; Muir, M.; Nousias, I.; Lindsay, Iain; Erdogan, A.T.

doi:10.1109/dasip.2010.5706249

Cited by 2 publications

(4 citation statements)

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“…The Dynamically Reconfigurable Asynchronous Processor (DRAP) [114], [115], is a processor based on novel clocked architecture called RICA [116]. The design main goal was to make an architecture that fulfill the demand of high-throughput mobile applications for energy efficiency and programmability using high-level languages.…”

Section: ) Drapmentioning

confidence: 99%

“…The DRAP processor consists of a heterogeneous array of course-grain asynchronous cells that are implemented using a reconfigurable data-path architecture. An abstract and comprehensive architecture view is presented in [114] and [117]. The design is based on operational cells where each interconnection of operational cells performs limited operations such as logic operation, addition and multiplication.…”

Section: ) Drapmentioning

confidence: 99%

“…Comparison of DRAP. Reprinted from[114].FIGURE 24.Block diagram of asynchronous neural signal processor. Reprinted from[126].…”

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confidence: 99%

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Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

et al. 2019

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Proceeding miniaturization in the VLSI circuits continues to pose challenges to the conventionally used synchronous design style in microprocessors. These include the distribution of clock in the GHz range, robustness to delay variations, reduction in electromagnetic interference, and energy conservation, to name a few. The asynchronous logic has been known for its ability to address the aforementioned challenges by means of the closed-loop handshake protocols, instead of notorious clock signals. Because of these advantages, there have been numerous attempts on building general and special purpose microprocessors during the last three decades. Still, however, the number of asynchronous processors commercially available is scarce, mainly due to an insufficient electronic design and automation tools support, an ambiguous design flow and testing mechanisms for asynchronous logic and, most importantly, absence of a forum to look for relevant works, explaining the design steps and tools for such microprocessors. This paper is intended to bridge this gap by 1) reviewing the design principles of asynchronous logic, including classification, signaling conventions, and pipelining approaches; 2) presenting the complete design flow and available electronic design and automation tools; 3) developing an encyclopedia of various general and special purpose microprocessors proposed by far; and 4) presenting an evaluation of those works in terms of area on the die and performance metrics. This paper will also serve as guidelines for the asynchronous microprocessor design and implementation in all phases from specification to tape-out.INDEX TERMS Asynchronous logic, electronic design and automation, microprocessor.

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Section: ) Drapmentioning

confidence: 99%

Section: ) Drapmentioning

confidence: 99%

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Towards Designing Asynchronous Microprocessors: From Specification to Tape-Out

et al. 2019

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“…High-throughput mobile applications increasingly demand programmability and energy efficiency [1][2] [3]. Until now, the choice of platform for such tasks has mostly been Application-Specific Integrated Circuits (ASICs), due to their best-ofbreed performance and power consumption.…”

Section: Introductionmentioning

confidence: 99%