A dual 23Gb/s CMOS transmitter/receiver chipset for 40Gb/s RZ-DQPSK and CS-RZ-DQPSK optical transmission

Cui, Delong; Raghavan, Bharath; Singh, Ullas; Vasani, Anand; Huang, Zhi; Pi, Deyi; Khanpour, M.; Nazemi, Ali; Maarefi, Hassan; Ali, Tamer; Huang, Nick; Zhang, Wei; Zhang, Bo; Momtaz, Afshin; Cao, Jun

doi:10.1109/isscc.2012.6177006

Cited by 7 publications

(2 citation statements)

References 5 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The VCO tuning range is from 20 to 29GHz with jitter of 0.23ps rms at 28.125GHz. The transceiver consumes 295mW (analog only) from a 1V supply (except TX LDO at 1.25V) per RX/TX, which is the lowest among published results for similar data-rate [2,3,5]. The die area is 0.62mm 2 per RX/TX, and a micrograph of four transceivers with PLL is shown in Fig.…”

mentioning

confidence: 90%

See 1 more Smart Citation

3.1 A 28Gb/s multi-standard serial-link transceiver for backplane applications in 28nm CMOS

Zhang

Khanoyan

Hatamkhani

et al. 2015

2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

Self Cite

View full text Add to dashboard Cite

Broadcom, Irvine, CA Rapid internet traffic growth has fueled the demand for bandwidth in metro networks and data centers and pushed the serial link data rate into 25Gb/s territory, populated by such electrical interface as OIF CEI-25G, CEI-28G [1], IEEE 802.3bj 100G-KR4. To cope with severe channel impairments at 25Gb/s with up to 30dB loss at Nyquist, a feed-forward equalizer (FFE)/decision feedback equalizer (DFE) based transceiver without power-hungry analog-todigital converter (ADC) provides robust performance. This work presents a low-power and area-efficient transceiver that employs a 14-tap adaptive DFE at the receiver (RX) and a 5-tap FFE at the transmitter (TX) for multi-standard applications up to 28Gb/s in 28nm CMOS.

show abstract

mentioning

confidence: 90%

“…A half-rate RX solution with unrolled Tap 1 [2][3][4][5] is the popular choice in high-speed DFE design. Tap 2 summing timing in an unrolled Tap 1 scheme becomes a performance-limiting factor due to an additional stage for Tap 1 MUX selection, typically a 4-stage delay.…”

mentioning

confidence: 99%