A DLL-Supported, Low Phase Noise Fractional-N PLL With a Wideband VCO and a Highly Linear Frequency Ramp Generator for FMCW Radars

Ng, Herman Jalli; Fischer, Alexander; Feger, Reinhard; Stuhlberger, R.; Maurer, Linus; Stelzer, Andreas

doi:10.1109/tcsi.2013.2265966

Cited by 47 publications

(17 citation statements)

References 20 publications

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“…Note that in [3] and [4] a prescaler is used before the MMD, so we normalized the chirp bandwidth by the prescaler divide ratio. Also for fair comparison we refer the frequency resolution and RMS frequency error to the VCO even if it is followed by a frequency multiplier as in [5]. We can see that we have the least RMS error while having the widest chirp bandwidth relative to the reference frequency.…”

Section: B Precision Simulationmentioning

confidence: 95%

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Fractional-N PLL optimization for highly linear wideband chirp generation for FMCW radars

El-Shennawy

Joram

Ellinger

2015

2015 German Microwave Conference

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This work addresses the optimization of Fractional-N Phase Locked Loops (Frac-N PLLs) used to produce frequency chirps for Frequency Modulated Continuous Wave (FMCW) radar applications. In a Frac-N PLL, we have two main clock domains which are the reference and the divided clock domains. Clock domain crossings have to be considered during chirp generation to produce highly linear chirps. Moreover, with wideband chirps, integer divide ratio increments during chirp generation may cause transient frequency glitches which also affect the chirp linearity if not taken care of. In this work we propose techniques to address these issues in Frac-N PLLs. The proposed techniques lead to highly linear wideband chirp generation and thus improve the distance calculation accuracy by a factor of 2 and the distance calculation precision by a factor of 1.5.

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Section: B Precision Simulationmentioning

confidence: 95%

“…This is mainly due to the required wide chirp bandwidth to achieve good range resolution [1,3,4,5]. In [2] we have introduced a Frac-N PLL that includes a wideband Voltage Controlled Oscillator (VCO) incorporating a single wide tuning range specially optimized for FMCW radar applications.…”

Section: Introductionmentioning

confidence: 99%

Fractional-N PLL optimization for highly linear wideband chirp generation for FMCW radars

El-Shennawy

Joram

Ellinger

2015

2015 German Microwave Conference

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“…For satisfying the LVDS specifications (Open LDI), the VCDL for the proposed DLL is made up of 14 delay cells. Among the multiphase signals coming from the VCDL, the signals from the odd delay stages (S[1]-S[7]) are used for sampling the input clock divided by two, and the signals from the even delay stages (PHA[1]-PHA [6]) are used for the FLD.…”

Section: Proposed Dll Architecturementioning

confidence: 99%

“…The works in [4] and [5] use a simple logic to prevent the false-lock problem but still depend on the duty ratio of the input clock. The DLL used in [6] improved the duty ratio independence and utilized multiphase clocks for an antifalse lock without an external reset signal for the PD. However, the antifalse-lock algorithm requires a complicated logic with less design flexibility.…”

Section: Introductionmentioning

confidence: 99%

A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

Moon

Kong

Ryu

et al. 2014

IEEE Trans. Circuits Syst. II

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This brief describes a wide-range operating falselock-free delay-locked loop (DLL) for a low-voltage differential signaling (LVDS) display interface. A false-lock detector circuit and a self-reset circuit internally prevent any possible false locks in a robust way. The proposed DLL immediately removes stuck false locks caused by an improper phase detector state. The DLL circuit does not require the duty ratio of the input clock to be 50%. The proposed circuit has been fabricated using the 0.15-μm 1P-6M mixed-mode CMOS technology. The proposed DLL is implemented for an LVDS display interface and supports operating from 20 to 135 MHz without any error. It consumes 2.2 mW under a 130-MHz operation.Index Terms-Complementary metal-oxide-semiconductor (CMOS), delay-locked loop (DLL), display interface, false lock, harmonic lock.

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“…ELAY-LOCKED loop (DLL)-based frequency multipliers have expanded their applications during the last decades into wireless communication systems [1]- [8]. Essential DLL characteristics such as the relatively wide loop-bandwidth, fast lock-in time, limited-accumulative jitter, and first-order stability, indicate the potentials of DLL-based frequency generation schemes [9].…”

Section: Introductionmentioning

confidence: 99%

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

Ojani

Mesgarzadeh

Alvandpour

2014

IEEE Trans. Circuits Syst. I

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Abstract-Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the outof-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of -45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.Index Terms-delay mismatch, DLL, duty cycle distortion, edge-combiner, frequency synthesizer, harmonic spur, periodic jitter, static phase error.

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A DLL-Supported, Low Phase Noise Fractional-N PLL With a Wideband VCO and a Highly Linear Frequency Ramp Generator for FMCW Radars

Cited by 47 publications

References 20 publications

Fractional-N PLL optimization for highly linear wideband chirp generation for FMCW radars

Fractional-N PLL optimization for highly linear wideband chirp generation for FMCW radars

A 2.2-mW 20–135-MHz False-Lock-Free DLL for Display Interface in 0.15- $\mu\hbox{m}$ CMOS

Modeling and Analysis of Harmonic Spurs in DLL-Based Frequency Synthesizers

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