Abstract-Periodic jitter raises the harmonic spurs at frequency synthesizer output spectrum, down-converting the outof-band interferers into the desired band and corrupting the wanted signal. This paper proposes a comprehensive behavioral model for spur characterization of edge-combining delay-locked loop (DLL)-based synthesizers, which includes the effects of delay mismatch, static phase error (SPE), and duty cycle distortion (DCD). Based on the proposed model and utilizing Fourier series representation of DLL output phases, an analytical model which formulates the synthesizer spur-to-carrier ratio (SCR) is developed. Moreover, from statistical analysis of the analytical derivations, a closed-form expression for SCR is obtained, from which a spur-aware synthesizer design flow is proposed. Employing this flow and without Monte Carlo (MC) method, one can determine the required stage-delay standard deviation (SD) of a DLL-based synthesizer, at which a certain spurious performance demanded by a target wireless standard is satisfied. A design example is presented which utilizes the proposed design flow to fulfill the SCR requirement of -45 dBc for WiMedia-UWB standard. Transistor-level MC simulation of the synthesizer SCR for a standard 65-nm CMOS implementation exhibits good compliance with analytical models and predictions.Index Terms-delay mismatch, DLL, duty cycle distortion, edge-combiner, frequency synthesizer, harmonic spur, periodic jitter, static phase error.
Abstract-This paper presents an 8-GS/s, 12-bit input ∆Σ DAC with 200-MHz bandwidth in 65-nm CMOS. The high sampling rate is achieved by a two-channel interleaved MASH 1-1 digital ∆Σ modulator with 3-bit output, resulting in a highly digital DAC with only seven current cells. The two-channel interleaving allows the use of a single clock for both the logic and the final multiplexing. This requires each channel to operate at half the sampling rate, which is enabled by a high-speed pipelined MASH structure with robust static logic. Measurement results show that the DAC achieves 200-MHz bandwidth, 26-dB SNDR and -57-dBc IMD3, with a power consumption of 68-mW at 1-V digital and 1.2-V analog supplies. This architecture shows potential for use in transmitter baseband for wideband wireless communication.
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