A dither-less all digital PLL for cellular transmitters

Vercesi, Luca; Fanori, Luca; Bernardinis, F. De; Liscidini, Antonio; Castello, R.

doi:10.1109/cicc.2011.6055301

Cited by 8 publications

(1 citation statement)

References 27 publications

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“…In order to correct for such random mismatch, several methods [6] have been proposed, that try to tune the delays of individual delay cells post fabrication, using "knobs" such as transistor widths (inside buffers), changing transistor thresholds by body biasing, and supply voltage biasing. But all these techniques suffer from the fact that they, (1) attempt to change delays of individual cells causing an increased calibration time and (2) are analog in nature and would therefore need good precision in controlling the "knobs."…”

Section: Introductionmentioning

confidence: 99%

All-digital replica techniques for managing random mismatch in time-to-digital converters

Sindia

Dai

Agrawal

2012

Proceedings of the 2012 44th Southeastern Symposium on System Theory (SSST)

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Abstract-We propose replica techniques with statistical post processing to improve integral non-linearity (INL) and code distribution performance of time-to-digital converters (TDC). We consider three different types of TDC namely: vernier delay line, multi-resolution, and ring oscillator based. We show that using a replica delay line with additional digital processing at the output, one can achieve better INL and code distribution (at every code) in each of the TDC architectures. The quantum of improvement is only limited by the additional hardware that is to be added, and can be traded for arbitrarily high improvements in INL and code distribution.

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Section: Introductionmentioning

confidence: 99%