A Dislocation Formation Model of Trench‐Induced Dislocations in Dynamic Random Access Memories

Abstract

In the early development of 4 megabit dynamic random access memories (4M DRAM5) with deep trench design some of the trench capacitor memory cells showed high charge leakage. This electrical failure was attributed to the occurrence of dislocations in the close vicinity of the trenches which were therefore termed trench-induced dislocations (TIDs). Process experiments revealed the stages and parameters influencing the TID formation and low-dislocation wafers were then produced. Systematic transmission electron microscope (TEM) analysis was performed on the wafers from the production experiment wafers. The TIDs showed a remarkable sequence of development throughout the different stages. Specific parameters having a major effect on the initial nucleation and subsequent propagation were identified. The combined results from the processing experiments and subsequent TEM examinations enabled a consistent model to be evolved in which the dry trench etching and the following oxidation processes played key roles, but not the ion implantations. InfroductionDislocations crossing p-n junctions have long been known to cause leakage currents' in semiconducting devices. Their harmful effects on memory devices such as DRAMs have been reported previously.2 In DRAMs the information is stored in memory cells, each of which is charged using a transistor; and due to unavoidable leakage this charge has to be restored periodically In faulty memory cells the charge is lost before the refresh cycle is completed.In most of the Siemens 4M DRAM devices the charge is stored in deep trenches of about 1 p.m in diam and 4 p.m in depth (Fig.1). In early releases some of these cells showed refresh failure, i.e., they needed very short refresh cycles, and this behavior was attributed to dislocations probably induced by the deep memory trenches. The dislocations were termed trench-induced dislocations (TIDs) and their densities were determined to be up to io cm2 using Secco-etching' after removal of the technology layers.Production experiments were carried out on two groups of test wafers. The first group was produced at constant conditions but up to different stages in the process. The second group was produced up to the same stage in the processing but with variation of process parameters.Portions of the wafers were then extensively investigated by optical microscopy after Secco-etching and by TEM. The results are described in the following. ExperimentalThe ability to hold a charge for a particular time was measured by the so-called refresh delay test. For this test cells were charged and this charge read out after increasingly longer periods of time. The number of cells failing to provide their original information after a given delay time was then obtained.For the determination of the dislocation densities, the surface technology layers of the wafers were removed by immersion in concentrated HF in an ultrasonic bath. After Fig. 1. SEM cross section of a 4M DRAM. ) unless CC License in place (see abstract). ecsdl.org/site/terms_use address. Redis...

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