A direct analog-to-residue converter

Radhakrishnan, D.; Preethy, A.P.

doi:10.1109/tencon.1998.798154

Cited by 2 publications

(4 citation statements)

References 2 publications

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“…The successive approximation based A/R converter (Radhakrishnan and Preethy 1999) has low area requirement but the conversion speed is k þ l þ 2 clock cycles, where 'k' and 'l' are the register size of the first and second stages. The iterative flash A/R converter (Radhakrishnan and Preethy 1998) is a compromise between the flash and SAR-based A/R converters by using the principle of subranging. The area complexity is medium for the iterative flash A/R converter.…”

Section: Decimation Filter Complexitymentioning

confidence: 99%

“…The total conversion time for this A/R converter is approximately k þ l þ 2 clock cycles. An iterative flash A/R converter is presented in Radhakrishnan and Preethy (1998), which uses the principle of subranging to reduce the hardware complexity of flash A/D converters. Here, the first stage flash converter is used iteratively to find the quotient of 'X' with respect to the largest moduli, m r .…”

Section: Introductionmentioning

confidence: 99%

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A novel Sigma–Delta based parallel analogue-to-residue converter

Shahana

Jose

Jacob

et al. 2009

International Journal of Electronics

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An important step in the residue number system (RNS) based signal processing is the conversion of signal into residue domain. Many implementations of this conversion have been proposed for various goals, and one of the implementations is by a direct conversion from an analogue input. A novel approach for analogue-to-residue conversion is proposed in this research using the most popular Sigma-Delta analogue-to-digital converter (SD-ADC). In this approach, the front end is the same as in traditional SD-ADC that uses Sigma-Delta (SD) modulator with appropriate dynamic range, but the filtering is done by a filter implemented using RNS arithmetic. Hence, the natural output of the filter is an RNS representation of the input signal. The resolution, conversion speed, hardware complexity and cost of implementation of the proposed SD based analogue-to-residue converter are compared with the existing analogue-to-residue converters based on Nyquist rate ADCs.Keywords: analogue-to-residue converter; Sigma-Delta modulator; decimation filter; residue number system; performance evaluation IntroductionMost of the real time digital signal processing (DSP) algorithms are based on intensive multiplication and addition operations. In real time systems digital convolution, finite impulse response (FIR) filtering, discrete Fourier transforms (DFT) and similar computations are at high sampling rate on long word lengths. The carry propagating multipliers and adders in binary number systems become the bottle-neck for high sampling rate computations. The use of residue number system (RNS) draws a great deal of interest in such computationally intensive DSP applications as it significantly speeds up multiply and accumulate (MAC) operations (Parhami 2000). Also, for higher orders and large dynamic range, the filters implemented in RNS are significantly smaller than filters implemented in the traditional two's complement number system (TCS). A design space exploration is carried out in Cardarilli, Ret, Nannarelli and Re (2007) to identify the trade offs between filters realised in TCS and RNS in terms of filter order, dynamic range, clock frequency and area. The nonpositional nature of RNS makes it suitable for fault-tolerant architectures. The error detection and correction properties are obtained by introducing few redundant moduli that are relatively prime to the non-redundant moduli. By including 'k' redundant moduli, it is possible to detect k errors and to correct bk/2c errors (Soderstrand,

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Section: Decimation Filter Complexitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A novel Sigma–Delta based parallel analogue-to-residue converter

Shahana

Jose

Jacob

et al. 2009

International Journal of Electronics

View full text Add to dashboard Cite

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“…With this method, the whole system is significantly simplified. Some research achievements in this area are published recently [2][3][4]. Most of these utilize ADC as a part of ARC.…”

Section: Introductionmentioning

confidence: 99%

“…The analog summer and multiple gain DAC limit the accuracy of the whole ARC. In [4], two Flash ADCs generate the quotient and the residue respectively. Both of the ARCs described in [3] and [4] require many high accuracy analog blocks, as such the area and power consumption are not optimized in the design.…”

Section: Introductionmentioning

confidence: 99%

A novel analog-to-residue converter for biomedical DSP application

Zhu

Huang

Lee

et al. 2012

2012 International SoC Design Conference (ISOCC)

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Digital Signal Processors (DSP) based on ResidueNumber System (RNS) are superior to conventional DSP especially in terms of parallel signal processing and power consumption. For modern state of the art biomedical applications, signal processing efficiency and robustness are of paramount importance. Therefore, the huge silicon overhead area and high power consumption of traditional Analog-to-Digital and Digital-to-Residue conversion scheme are not feasible to be used in the field of biomedical science. Therefore, direct Analog-to-Residue conversion begins to attract immense interest from many researchers and engineers in the world today. In this paper, a new method to realize the direct Analogto-Residue conversion is presented. This method shows a promising characteristic for low power and process scaling via utilizing time as the intermediate method in the processing.I.

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A direct analog-to-residue converter

Cited by 2 publications

References 2 publications

A novel Sigma–Delta based parallel analogue-to-residue converter

A novel Sigma–Delta based parallel analogue-to-residue converter

A novel analog-to-residue converter for biomedical DSP application

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