A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones

Abstract

We propose and demonstrate the first RF digitally controlled oscillator (DCO) for cellular mobile phones. The DCO is part of a single-chip quad-band fully compliant GSM transceiver realized in a 90 nm digital CMOS process. Wide and precise linear frequency tuning is achieved through digital control of a large array of standard n-poly/n-well MOSCAP devices that operate in flat regions of their C-V curves. The varactors are partitioned into binary-weighted and unit-weighted banks that are sequentially activated during frequency locking and tracking. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz high-band output. To attenuate the quantization noise to below the natural oscillator phase noise, the varactors undergo high-speed second-order 61 dithering. We analyze the effect of the 61 dithering on the phase noise and show that it can be made sufficiently small. The measured phase noise at 20 MHz offset in the GSM900 band is 165 dBc/Hz and shows no degradation due to the 61 dithering. The 3.6 GHz DCO core consumes 18.0 mA from a 1.4 V supply and has a very wide tuning range of 900 MHz to support the quad-band operation.

A 60GHz digitally controlled phase shifter in CMOS

“…The phase shifter consists of a differential transmission line loaded with and a differential MOS varactor at each side. The cross-sectional view of a differential MOS varactor is shown in Figure 3 [18]. The top and bottom plates of the varactor are formed by the poly gates and n-well.…”

Design of Gigahertz Tuning Range 5 GHz LC Digitally Controlled Oscillator in 0.18 μm CMOS

“…Former type of PLL is getting more attention in recent years, since it becomes harder to design analog blocks in advancing CMOS technologies, due to reduced supply voltage, increasing impact of leakage currents. Also, it is faster and easier to redesign all-digital PLL in different technology [1][2][3][4].…”

Applications of On-Chip Coplanar Waveguides to Design Local Oscillators for Wireless Communications System

“…An oscillator, being a critical component of all digital phase locked loop (ADPLL) for future generation wireless transceiver, is necessary to be implemented using digital signals to control its frequency tuning characteristics. Recently, various types of DCO architectures were proposed and implemented in deep submicron CMOS technology (Staszewski et al, 2005, Fahs et al, 2009). The DCO implemented in ring structure (Fahs et al, 2009) gives poor phase noise performance with high power consumption, and they are, therefore, hardly suitable for multi-GHz wireless applications.…”

“…The DCO implemented in ring structure (Fahs et al, 2009) gives poor phase noise performance with high power consumption, and they are, therefore, hardly suitable for multi-GHz wireless applications. In a DCO implemented using a LC-resonator (Staszewski et al, 2005), on-chip inductor (L) is inherent which increases the chip size and in turn, results in high price. In this Section, we will propose a 10bit DCO using on-chip CPW resonator and MIM capacitors instead of the LC-resonator.…”