The intelligent transport system (ITS) has become one of the most globally researched topics with a lot of investment and development resources being dedicated into it due to its foreseen impact on the economic growth of the transport sector. Currently there are two main vehicle-to-everything (V2X) technologies, whose primary application is focused on ITS, backed up by the key players of various automotive, telecommunication and transport industries: dedicated short-range communications (DSRC) and cellular vehicle-to-everything (C-V2X), respectively based on IEEE 802.11p and 3GPP LTE/5G NR. While DSRC already has deployments, C-V2X is expected to see larger scale trails and deployments in 2020. In this work, the authors provide insight and review into two main V2X technologies, DSRC and C-V2X, their core parameters, shortcomings and limitations, and explore the need for integration of IoT-based technologies into modern ITS solutions. A comprehensive overview and analysis of currently commercially available V2X products, their sub-blocks and features is provided.
In recent years number of Internet of Things (IoT) services and devices is growing and Internet of Vehicles (IoV) technologies are emerging. Multiband transceiver with high performance frequency synthesisers should be used to support a multitude of existing and developing wireless standards. In this paper noise sources of an all-digital frequency synthesiser are discussed through s-domain model of frequency synthesisers, and the impact of noise induced by main blocks of synthesisers to the overall phase noise of frequency synthesisers is analysed. Requirements for time to digital converter (TDC), digitally controlled oscillator (DCO) and digital filter suitable for all-digital frequency synthesiser for IoT and IoV applications are defined. The structure of frequency synthesisers, which allows us to meet defined requirements, is presented. Its main parts are 2D Vernier TDC based on gated ring oscillators, which can achieve resolution close to 1 ps; multi core LC-tank DCO, whose tuning range is 4.3–5.4 GHz when two cores are used and phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier; digital filter made of proportional and integral gain stages and additional infinite impulse response filter stages. Such a structure allows us to achieve a synthesiser’s in-band phase noise lower than −100 dBc/Hz, out-of-band phase noise equal to −134.0 dBc/Hz and allows us to set a synthesiser to type-I or type-II and change its order from first to sixth.
In this paper design and simulation of a 4.3 -5.4 GHz LC digitally controlled oscillator (LC DCO) in IBM 7RF 0.18 µm CMOS technology are presented. Wide gigahertz tuning range is achieved by using two LC DCOs, sharing same structure. DCO is made of one NMOS negative impedance transistor pair and LC tank, which consists of high quality inductor and two switched capacitor arrays for coarse and fine frequency tuning. Coarse and fine tuning switched capacitor arrays are controlled using 6-bit and 3-bit binary words. To increase available frequency values, frequency divider is used. Structure of frequency divider is based on extended-true-single-phase-clock flip-flops. Divider is made of eight divide-by-2 cells connected in daisy chain, thus division values from 2 to 256 are available. Wide tuning range and high division values allows using such DCO with frequency divider in multi-standart transceivers. Whole device is supplied from a single 1.8 V voltage source. At highest frequency proposed device draws 90 mA current including all buffers. Phase noise is −116.4 dBc/Hz at 1 MHz offset from 5.44 GHz carrier. Designed dual DCO and frequency divider occupies about 0.4 mm × 0.5 mm of chip space and whole chip, including pads, occupies 1.5 mm × 1.5 mm area of silicon.K e y w o r d s: CMOS, integrated circuit, high frequency, digitally controlled oscillator, frequency divider, extended true-single-phase-clock
Parameters of integrated analog filters can vary due to temperatu-re change, IC process variation and therefore they should have dedicated tuning circuits that compensate these imperfections. A method is proposed that speeds up switched resistor bank design while taking into account the required tuning range and step size. A novel counter structure is used in the tuning circuit that is ba-sed on successive approximation approach. The proposed swit-ched resistor design method and tuning circuit are designed in 0.18 μm CMOS technology and verified. Results are compared to existing tuning circuit designs. Integrinių analoginių filtrų parametrai gali kisti dėl temperatūros, senėjimo ar integrinių grandynų gamybos procesų netolydumo. Todėl jiems būtina numatyti papildomus grandynus, kurie kompensuotų filtrų komponentų pokyčius. Darbe siūlomas naujas integrinių aktyviųjų RC filtrų perjungiamų rezistorių matricų projektavimo metodas, kuris leidžia kompensuoti pasyvių komponentų nuokrypius ir užtikrina filtro praleidžiamų dažnių juostos derinimą reikiamu žingsniu. Savaiminio derinimo sistemoje remiamasi nauja skaitiklio architektūra, kuri naudoja nuosekliosios aproksimacijos paieškos algoritmą. Darbe pasiūlytas projektavimo metodas tikrinamas projektuojant filtro derinimo sistemą, naudojant 0,18 μm KMOP integrinių grandynų gamybos technologiją ir Cadence Virtuoso programinę įrangą. Gauti rezultatai palyginami su literatūroje pateiktais derinimo sistemų skaičiavimų rezultatais.
In this paper, an oscillation-based built-in self-test system for active an analog integrated circuit is presented. This built-in self-test system was used to detect catastrophic and parametric faults, introduced during chip manufacturing. As circuits under test (CUT), second-order Sallen-Key, Akerberg-Mossberg and Tow-Thomas biquad filters were designed. The proposed test hardware detects parametric and catastrophic faults on changeable limits. The influence of both oscillation and test hardware on fault detection limits were investigated and analyzed. The proposed oscillation based self-test system was designed and simulated in 0.18 µm complementary metal-oxide semiconductor (CMOS) technology. Due to the easiness of implementation and configuration for testing of different active analog filters, such self-test systems can be effectively used in modern integrated circuits, made of a large number of devices and circuits, such as the multi-standard transceivers used in the core hardware of software-defined radios. Using the proposed test strategy, the fault tolerance limits for catastrophic faults varied from 96% to 100% for all injected faults in different structures of low pass filters (LPF). The detection range of parametric faults of passive components’ nominal value, depending on the used structure of the filter, did not exceed –0.74% – 0.72% in case of Sallen-Key, –3.31% – 1.00% in case of Akerberg-Mossberg and –2.39% – 1.44% in case of Tow-Thomas LPF.
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