A Digital System Design Language (DDL)

The paper describes and compares three different designs for a high-speed two's-complement, fullyserial tree multiplier, the first of which uses a correction technique, the second Booth's algorithm, and the third employs sign extension. All three designs, each of which possess advantages for different applications, may be clocked at the ceiling frequency determined by the delay through an adder and a flip-flop. Each design was simulated functionally at the gate level, an exercise that revealed several shortcomings and redundancies in what had been considered to be an optimal design. The importance of simulation for design verification in such cases is stressed and a straightforward method for accomplishing it, based on a synchronousstate machine approach and using a general-purpose language (Pascal), is presented. IntroductionWith the recent growth of interest in digital communication, serial-processing techniques have become popular for analysing and manipulating word-formatted serial digital information. In particular, serial correlation may be employed for the insertion of control bits to monitor and correct codes [1], for the insertion of word and frame synchronisation information [1] and for data scrambling and unscrambling [2]. The majority of such correlation techniques which are currently in use employ parallel computation, but the ability to process 'on the fly' without having to resort to parallel-to-serial and serial-to-parallel conversion has obvious advantages. Several series/parallel multiplier chips are available commercially, such as the Am25LS14 [3], which is a cascadable 8-bit by 1-bit multiplier, where the multiplier is presented in parallel and the multiplicand bits are supplied serially. The whole operation requires 2n clock pulses where n is the word length. Such multipliers find use in applications such as scaling by a constant, but for the correlation applications such as those mentioned above, if fully serial processing is desired, then a multiplier where both multiplier and multiplicand are presented serially is required; and to this end the serial tree multiplier [4] is particularly suitable.The design presented in Reference 4, however, handles unsigned numbers only, and this paper considers three different ways in which the serial tree multiplier may be modified to handle two's-complement numbers.Each of the designs is then subjected to a rigorous functional simulation at the gate level, an exercise that revealed several shortcomings and redundances in what had been originally considered to be a correct and optimal design. The method used involves modelling the circuit as a synchronous-state machine using a general-purpose highlevel language -in this case Pascal -and exercising the model for all possible input combinations.One possible reason why design verification through functional simulation is not more widely used is the deterrent of having to learn and become familiar with a new language -and indeed the choice of language from the numerous simulation languages that exist. This pa...

show abstract

“…PMS [6]), through 'register-transfer' level (e.g. ISP [6], DDL [7]), to circuit level (e.g. SCEPTRE [8]).…”

Section: Description and Simulation Languagesmentioning

confidence: 99%

Design of high-speed fully serial tree multiplier

McCrea

Matheson

1981

IEE Proc. E Comput. Digit. Tech. UK

View full text Add to dashboard Cite

show abstract

“…[2][3][4][5][6] However, the manner in which the modelling approaches have been combined has caused ambiguity and excessive complexity in the resulting languages.…”

Section: Introductionmentioning

confidence: 99%

“…Algorithmic based languages such as Chu's [5] language are satisfactory when decribing system behavior but lack precision when specifying details of system structure and control. Duley and Dietmeyer's D~L [6] generally meets most of the requirements, however, it is felt that DDL is somewhat complex in terms of ease of learning and length of retention.…”

Section: Introductionmentioning

confidence: 99%

A digital system modeling philosophy and design language

Baray¹,

Su²

1971

Proceedings of the June 1971 Design Automation Workshop on Design Automation - DAC '71

View full text Add to dashboard Cite

show abstract

“…Duley and Dietmeyer (8,9) informally proposed a language for a system of finite automata each having private facilities (registers, memories, etc.) and sharing public facilities.…”

Section: Chapter Ii-literature Reviewmentioning

confidence: 99%

“…The language's provision for describing the serial, parallel and a combination of serial and parallel events allows the designer a greater degree of freedom than previously offered. Most other languages (6,8,21,25) allow for only parallel execution of actions and one allows for a limited form of parallel execution of serial events (2,3). This feature, in and of itself, allows the designer to describe when the multitude of events are to occur within the system more accurately.…”

Section: Chapter IX Conclusionmentioning

confidence: 99%

A language to describe and simulate multiprocessor computer systems

Elliott

View full text Add to dashboard Cite

A Digital System Design Language (DDL)

Cited by 72 publications

References 13 publications

Design of high-speed fully serial tree multiplier

Design of high-speed fully serial tree multiplier

A digital system modeling philosophy and design language

A language to describe and simulate multiprocessor computer systems

Contact Info

Product

Resources

About